{"title":"Correlation between MR-DCIV current and high-voltage-stress-induced degradation in LDMOSFETs","authors":"Yandong He, Lin Han, Ganggang Zhang, Xing Zhang","doi":"10.1109/ISPSD.2013.6694426","DOIUrl":null,"url":null,"abstract":"MR-DCIV current has demonstrated the nondestructive capability to profile the interface states along the channel, accumulation and STI regions in high-voltage LDMOSFET. The correlation between interface state and MR-DCIV current has been studied under high voltage stresses in LDMOSFETs. Our study results show that RON degradation is mainly affected by newly-generated interface states in the STI region. Compare to the PBTI with higher gate voltage, OFF-state stress with higher drain voltage would become the worst degradation condition in an STI-based nLDMOSFETs.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2013.6694426","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
MR-DCIV current has demonstrated the nondestructive capability to profile the interface states along the channel, accumulation and STI regions in high-voltage LDMOSFET. The correlation between interface state and MR-DCIV current has been studied under high voltage stresses in LDMOSFETs. Our study results show that RON degradation is mainly affected by newly-generated interface states in the STI region. Compare to the PBTI with higher gate voltage, OFF-state stress with higher drain voltage would become the worst degradation condition in an STI-based nLDMOSFETs.
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