{"title":"On using ATPG vectors for BIST TPG","authors":"T. Asakawa, K. Iwasaki","doi":"10.1109/APASIC.1999.824104","DOIUrl":null,"url":null,"abstract":"We propose a method for designing a test pattern generator (TPG) to achieve high-fault coverage for stuck-at faults with short application time during BIST. The TPG consists of shift registers and a small amount of ROM containing test vectors generated by an ATPG tool. Experimental results show that our method can drastically reduce the test length required to achieve high-fault coverage with a small amount of hardware overhead in comparison with an LFSR-based method.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824104","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
We propose a method for designing a test pattern generator (TPG) to achieve high-fault coverage for stuck-at faults with short application time during BIST. The TPG consists of shift registers and a small amount of ROM containing test vectors generated by an ATPG tool. Experimental results show that our method can drastically reduce the test length required to achieve high-fault coverage with a small amount of hardware overhead in comparison with an LFSR-based method.
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