N. Okazaki, F. Miyaji, K. Kobayashi, Y. Harada, J. Aoyama, T. Shimada
{"title":"A 30ns 256K full CMOS SRAM","authors":"N. Okazaki, F. Miyaji, K. Kobayashi, Y. Harada, J. Aoyama, T. Shimada","doi":"10.1109/ISSCC.1986.1156880","DOIUrl":null,"url":null,"abstract":"This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm× 13.2μm.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm× 13.2μm.
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