Power bus maximum voltage drop in digital VLSI circuits

Abstract

This paper presents a new input-independent method for finding the maximum voltage drop of the power bus in digital VLSI circuits. The method relies on expressing the voltage at the power bus nodes in terms of gate currents using sensitivity analysis. Circuit timing information and circuit functionality are used to find maximum simultaneous switching and upper bounds on maximum voltage drop at a given node over a clock cycle. The effects of primary inputs misalignment and statistical variation in the circuit delays on maximum voltage drop are automatically included in our method. HSPICE exhaustive simulation results on 3 by 3 and 4 by 4 multipliers are used to validate our work.