A Low-Power Successive Approximation Analog-to-Digital Converter Based on 2-Bit/Step Comparison

Abstract

A novel low-power 8-bit successive approximation (SA) ADC using multiple-valued approach is presented. In contrast to conventional 1bit/step SA ADCs, 2bit/step conversion is employed, and combined with the split capacitor array and dual sampling technique to reduce the power consumption. Transistor level simulation, assuming 0.18-µm standard CMOS technology, shows that the total power consumption decreases by about 20% compared with that obtained for a 1bit/step counterpart at a sampling frequency of 100 kHz. Since the digital part consumes more power than the analog part, the present approach is expected to be more attractive for ADCs using advanced process technology.