In this paper we examine different possibilities of defining reduced products and ultraproducts in fuzzy predicate logics. We present analogues to the $L$os Theorem for these notions and discuss the advantages and drawbacks of each definition introduced. Following the work in cite{De09}, we show that these constructions are adequate for working in a reduced semantics
{"title":"Revisiting Ultraproducts in Fuzzy Predicate Logics","authors":"Pilar Dellunde","doi":"10.1109/ISMVL.2010.33","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.33","url":null,"abstract":"In this paper we examine different possibilities of defining reduced products and ultraproducts in fuzzy predicate logics. We present analogues to the $L$os Theorem for these notions and discuss the advantages and drawbacks of each definition introduced. Following the work in cite{De09}, we show that these constructions are adequate for working in a reduced semantics","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124577246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In spite of the multiplication of truth-values, a noticeable shade of bivalence lurks behind the canonical notion of entailment that many-valued logics inherit from the 2-valued case. Can this bivalence be somehow used to our advantage? The present note briefly surveys the progress made in the last three decades toward making that theme precise from an abstract point of view and extracting some useful procedures from it, harvesting some of its most favorable crops on the domains of semantics and proof-theory.
{"title":"Two Many Values: An Algorithmic Outlook on Suszko's Thesis","authors":"Carlos Caleiro, J. Martin Marcos","doi":"10.1109/ISMVL.2010.25","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.25","url":null,"abstract":"In spite of the multiplication of truth-values, a noticeable shade of bivalence lurks behind the canonical notion of entailment that many-valued logics inherit from the 2-valued case. Can this bivalence be somehow used to our advantage? The present note briefly surveys the progress made in the last three decades toward making that theme precise from an abstract point of view and extracting some useful procedures from it, harvesting some of its most favorable crops on the domains of semantics and proof-theory.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124749121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we review the Billiard Ball Model (BBM) introduced by Toffoli and Fredkin. The analysis of a previous approach to design reversible networks based on BBM it shown to ignored physical realities. We prove that some logic function cannot be realized without additional control balls. For example, to realize the logical OR operation, at least three control balls are needed. We show how reversible Toffoli gates can be constructed with this model. Finally, a Toffoli gate module is proposed that can be used in a cascade of gates and thus implement arbitrary reversible functions.
{"title":"Toffoli Gate Implementation Using the Billiard Ball Model","authors":"Hadi Hosseini, G. Dueck","doi":"10.1109/ISMVL.2010.40","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.40","url":null,"abstract":"In this paper we review the Billiard Ball Model (BBM) introduced by Toffoli and Fredkin. The analysis of a previous approach to design reversible networks based on BBM it shown to ignored physical realities. We prove that some logic function cannot be realized without additional control balls. For example, to realize the logical OR operation, at least three control balls are needed. We show how reversible Toffoli gates can be constructed with this model. Finally, a Toffoli gate module is proposed that can be used in a cascade of gates and thus implement arbitrary reversible functions.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114668275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes an algorithm that determines the minimal sets of variables that determine the values of a discrete partial function. The algorithm is based on the notion of entropy of a partition and is able to achieve an optimal solution. A limiting factor is introduced to restrict the search, thereby providing the option to reduce running time. Experimental results are provided that demonstrate the efficiency of the algorithm for functions with up to 24 variables. The effect of the limiting factor on the optimality of the algorithm for different sizes of partial functions is also examined.
{"title":"Information-Theoretical Mining of Determining Sets for Partially Defined Functions","authors":"D. Simovici, D. Pletea, R. Vetro","doi":"10.1109/ISMVL.2010.61","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.61","url":null,"abstract":"This paper describes an algorithm that determines the minimal sets of variables that determine the values of a discrete partial function. The algorithm is based on the notion of entropy of a partition and is able to achieve an optimal solution. A limiting factor is introduced to restrict the search, thereby providing the option to reduce running time. Experimental results are provided that demonstrate the efficiency of the algorithm for functions with up to 24 variables. The effect of the limiting factor on the optimality of the algorithm for different sizes of partial functions is also examined.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116856800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a consequence relation for graded inference within the frame of infinite-valued Lukasiewicz semantics. We consider the premises to be true to at least a certain degree A and consider as consequences those sentences entailed to have a degree of truth at least some suitable threshold B. We focus on the study of some aspects and features of the consequence relation presented and, in particular, on the effect of variations in the thresholds A, B.
{"title":"A Graded Inference Approach Based on Infinite-Valued Lukasiewicz Semantics","authors":"David Picado Muiño","doi":"10.1109/ISMVL.2010.54","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.54","url":null,"abstract":"We present a consequence relation for graded inference within the frame of infinite-valued Lukasiewicz semantics. We consider the premises to be true to at least a certain degree A and consider as consequences those sentences entailed to have a degree of truth at least some suitable threshold B. We focus on the study of some aspects and features of the consequence relation presented and, in particular, on the effect of variations in the thresholds A, B.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Stankovic, J. Astola, D. M. Miller, R. Stankovic
Spectral techniques on Abelian groups are a well-established tool in diverse fields such as signal processing, switching theory, multi-valued logic and logic design. The harmonic analysis on finite non-Abelian groups is an extension of them, which has also found applications for particular tasks in the same fields. It takes advantages of the peculiar features of the domain groups and their dual objects. Representing unitary irreducible representations, that are kernels of Fourier transforms on non-Abelian groups, in a compact manner is a key task in this area. These representations are usually specified in terms of rectangular matrices with matrix entries. Therefore, the problem of their efficient representations can be viewed as handling large rectangular matrices with matrix-valued entries. Quantum Multiple-valued Decision Diagrams (QMDDs) and Heterogeneous Decision Diagrams (HDDs) have been used for representation of matrices with numerical values, under some restrictions to the order of matrices to be represented. In this paper, we present a generalization of this concept for the representation of rectangular matrices with matrix-valued entries. We also demonstrate an implementation of an XML-based software package aimed at handling such data structures.
{"title":"Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian Groups","authors":"S. Stankovic, J. Astola, D. M. Miller, R. Stankovic","doi":"10.1109/ISMVL.2010.63","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.63","url":null,"abstract":"Spectral techniques on Abelian groups are a well-established tool in diverse fields such as signal processing, switching theory, multi-valued logic and logic design. The harmonic analysis on finite non-Abelian groups is an extension of them, which has also found applications for particular tasks in the same fields. It takes advantages of the peculiar features of the domain groups and their dual objects. Representing unitary irreducible representations, that are kernels of Fourier transforms on non-Abelian groups, in a compact manner is a key task in this area. These representations are usually specified in terms of rectangular matrices with matrix entries. Therefore, the problem of their efficient representations can be viewed as handling large rectangular matrices with matrix-valued entries. Quantum Multiple-valued Decision Diagrams (QMDDs) and Heterogeneous Decision Diagrams (HDDs) have been used for representation of matrices with numerical values, under some restrictions to the order of matrices to be represented. In this paper, we present a generalization of this concept for the representation of rectangular matrices with matrix-valued entries. We also demonstrate an implementation of an XML-based software package aimed at handling such data structures.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124008809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.
{"title":"Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors","authors":"Yuichi Baba, N. Homma, A. Miyamoto, T. Aoki","doi":"10.1109/ISMVL.2010.20","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.20","url":null,"abstract":"This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130064789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques often implies non-standard methods that are not supported by the conventional design tools. In the recent decade the designers of secure devices have been working hard on customising the workflow. The presented research aims to collect the up-to-date experiences in this area and create a generic approach to the secure design flow that can be used as guidance by engineers. In the presented paper the emphasis is put on multi-valued logic synthesis and asynchronous system design. The proposed flow employs the tool based on higher radix and mixed radix Reed-Muller expansions, power-balanced logic component libraries and TiDE design environment. The challenge of the research here is interfacing between different EDA tools and technologies. An example is also presented and described from the view of the system designer.
{"title":"Secure Design Flow for Asynchronous Multi-valued Logic Circuits","authors":"A. Rafiev, Julian P. Murphy, A. Yakovlev","doi":"10.1109/ISMVL.2010.56","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.56","url":null,"abstract":"The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques often implies non-standard methods that are not supported by the conventional design tools. In the recent decade the designers of secure devices have been working hard on customising the workflow. The presented research aims to collect the up-to-date experiences in this area and create a generic approach to the secure design flow that can be used as guidance by engineers. In the presented paper the emphasis is put on multi-valued logic synthesis and asynchronous system design. The proposed flow employs the tool based on higher radix and mixed radix Reed-Muller expansions, power-balanced logic component libraries and TiDE design environment. The challenge of the research here is interfacing between different EDA tools and technologies. An example is also presented and described from the view of the system designer.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121678365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Additional lines are required to implement an irreversible function as a reversible circuit. The emphasis, particularly in automated synthesis methods, has been on using the minimal number of additional lines. In this paper, we show that circuit cost reductions can be achieved by adding additional lines. We present an algorithm for line addition that can be targeted to reducing the quantum cost of a circuit or the transistor count for a CMOS implementation. Experimental results show that the cost reduction can be significant even if (1) only a small number of lines (even one) is added and (2) other circuit optimizations have already been applied.
{"title":"Reducing Reversible Circuit Cost by Adding Lines","authors":"D. M. Miller, R. Wille, R. Drechsler","doi":"10.1109/ISMVL.2010.48","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.48","url":null,"abstract":"Additional lines are required to implement an irreversible function as a reversible circuit. The emphasis, particularly in automated synthesis methods, has been on using the minimal number of additional lines. In this paper, we show that circuit cost reductions can be achieved by adding additional lines. We present an algorithm for line addition that can be targeted to reducing the quantum cost of a circuit or the transistor count for a CMOS implementation. Experimental results show that the cost reduction can be significant even if (1) only a small number of lines (even one) is added and (2) other circuit optimizations have already been applied.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132364164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Following an “unwritten tradition” this paper offers a review of another decade of achievements in the area of Spectral Techniques. Topics like transforms of matrix-valued functions, transforms based on non-Abelian groups, latest advancements related to Linear Independent transforms, a space-efficient algorithm to calculate spectral transforms, will be discussed. A special mention will be given to other areas, like signal processing, and coding theory, where Spectral Techniques have been (and continue to be) used, even though with possibly different names.
{"title":"Spectral Techniques: The First Decade of the XXI Century (Invited Paper)","authors":"C. Moraga","doi":"10.1109/ISMVL.2010.10","DOIUrl":"https://doi.org/10.1109/ISMVL.2010.10","url":null,"abstract":"Following an “unwritten tradition” this paper offers a review of another decade of achievements in the area of Spectral Techniques. Topics like transforms of matrix-valued functions, transforms based on non-Abelian groups, latest advancements related to Linear Independent transforms, a space-efficient algorithm to calculate spectral transforms, will be discussed. A special mention will be given to other areas, like signal processing, and coding theory, where Spectral Techniques have been (and continue to be) used, even though with possibly different names.","PeriodicalId":447743,"journal":{"name":"2010 40th IEEE International Symposium on Multiple-Valued Logic","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115679392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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