New tools and methodology for advanced parametric and defect structure test

Abstract

Continuing scaling trends in semiconductor technology, as well as the test requirements of new technologies being incorporated with mainstream silicon integrated circuits, has increased the complexity of parametric and defect structure testing. New testers are required which can drastically improve the throughput of parametric test, as well as efficiently test new array based process diagnostic structures. Addressing these needs requires merging the traditionally separate functions of digital and parametric test equipment. We describe the development of a new hybrid test system, which combines the features of parametric and digital testers, and in addition introduces a high degree parallelism in its parametric test functions. The test system was developed for high throughput inline test (“parallel test”) of defect structures, semiconductor parametric macros, and advanced array based process monitors down to pA current levels, as well as traditional all digital yield macros, such as SRAMs.