On-Chip Lifetime Prediction for Dependable Many-Processor SoCs Based on Data Fusion

Abstract

The developments in technology and complexity of many-processor Systems-on-Chips emerge at a very rapid pace as is their introduction in safety-critical applications, for instance the transport sector. The inherent decrease in dependability of these complex nanosystems must be compensated by counter measures. One promising approach is the usage of IJTAG-compatible embedded instruments in and around cores, monitoring the "health" of target processors. It has been anticipated that these instruments will be (primarily) used for reducing the cost of final testing. In case of degradation during life time, however, they can be reused and counteractions like run-time remapping can be carried out. In this paper, the on-line data of two types of embedded instruments will be used for the prognostics, a slack-delay monitor and an IDDX monitor. Their (correlated) data is being fused which enables a more accurate life-time prediction as compared to a single monitor approach. However, the computational requirements for the embedded dependability manager will increase to enable handling embedded instrument data fusion and/or multi-parameter life-time prediction