Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00037
Vanchinathan Venkataramani, A. Pathania, M. Shafique, T. Mitra, J. Henkel
Workloads from autonomous systems project an unprecedented processing demand onto their underlying embedded processors. Workload comprises of an ever-changing mix of multitudes of sequential and parallel tasks. Adaptive many-core processors with their immense yet flexible processing potential are up to the challenge. Adaptive many-core house together tens of base cores capable of forming more complex cores at run-time. Adaptive many-cores, therefore, can accelerate both sequential and parallel tasks whereas non-adaptive many-cores can only accelerate the latter. Adaptive many-cores can also reconfigure themselves to conform to the needs of any workload whereas non-adaptive many-cores - homogeneous or heterogeneous - are inherently limited given their immutable design. The accompanying qualitative schedule is the key to achieving the real potential of an adaptive many-core. The scheduler must move base cores between tasks on the fly to meet the goals of the overlying autonomous system. The scheduler also needs to scale up with the increase in the number of cores in adaptive many-cores without making compromises on the schedule quality. We present a nearoptimal distributed scheduler for maximizing performance on adaptive many-cores. We also introduce an online performance prediction technique for adaptive many-cores that enable the proposed scheduler to operate without any task profiling.
{"title":"Scalable Dynamic Task Scheduling on Adaptive Many-Core","authors":"Vanchinathan Venkataramani, A. Pathania, M. Shafique, T. Mitra, J. Henkel","doi":"10.1109/MCSoC2018.2018.00037","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00037","url":null,"abstract":"Workloads from autonomous systems project an unprecedented processing demand onto their underlying embedded processors. Workload comprises of an ever-changing mix of multitudes of sequential and parallel tasks. Adaptive many-core processors with their immense yet flexible processing potential are up to the challenge. Adaptive many-core house together tens of base cores capable of forming more complex cores at run-time. Adaptive many-cores, therefore, can accelerate both sequential and parallel tasks whereas non-adaptive many-cores can only accelerate the latter. Adaptive many-cores can also reconfigure themselves to conform to the needs of any workload whereas non-adaptive many-cores - homogeneous or heterogeneous - are inherently limited given their immutable design. The accompanying qualitative schedule is the key to achieving the real potential of an adaptive many-core. The scheduler must move base cores between tasks on the fly to meet the goals of the overlying autonomous system. The scheduler also needs to scale up with the increase in the number of cores in adaptive many-cores without making compromises on the schedule quality. We present a nearoptimal distributed scheduler for maximizing performance on adaptive many-cores. We also introduce an online performance prediction technique for adaptive many-cores that enable the proposed scheduler to operate without any task profiling.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115686152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00032
Hyeongyun Moon, Jeonghun Cho, Daejin Park
IoT systems, which are connected with irregular links between heterogeneous things, are vulnerable to fast error propagation caused by unwanted abnormal statuses. We often add system monitoring circuits to protect against unresolved freezing due to this problem. However, practical approaches in the field result in the over-specification of designs to cover all unknown problems, so that a large amount of additional power is consumed. In this paper, we adopt two ways to solve this problem efficiently: the effective reconfiguration of power state parameters for the low-power operations of embedded hardware and software in a communication-centric system-on-chip (SoC), and a design-space-exploration framework under the large-scale construction of irregular links between the processors. Given the large-scale connection of SoCs for the experiment, the system can be safely operated with a very wide monitoring active cycle, and power consumption can also be reduced.
{"title":"Freeze-Safe IoT Hibernation using Power Profile Monitor Based on Communication-Centric Auto-Tuning","authors":"Hyeongyun Moon, Jeonghun Cho, Daejin Park","doi":"10.1109/MCSoC2018.2018.00032","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00032","url":null,"abstract":"IoT systems, which are connected with irregular links between heterogeneous things, are vulnerable to fast error propagation caused by unwanted abnormal statuses. We often add system monitoring circuits to protect against unresolved freezing due to this problem. However, practical approaches in the field result in the over-specification of designs to cover all unknown problems, so that a large amount of additional power is consumed. In this paper, we adopt two ways to solve this problem efficiently: the effective reconfiguration of power state parameters for the low-power operations of embedded hardware and software in a communication-centric system-on-chip (SoC), and a design-space-exploration framework under the large-scale construction of irregular links between the processors. Given the large-scale connection of SoCs for the experiment, the system can be safely operated with a very wide monitoring active cycle, and power consumption can also be reduced.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134282561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00018
K. Pham, E. Horta, Dirk Koch, Anuj Vaishnav, T. Kuhn
SRAM-based FPGA devices have been used widely in many industrial domains, but only limitedly in secure and safety-critical applications, which have special requirements for the physical implementation, such as module isolation. This is partly due to limited functionality available with current FPGA vendors' tools and flows. To extend FPGA's appearance in secure and safety-critical applications, we propose an alternative flow for isolation design called the Isolated Partial Reconfiguration Design Flow (IPRDF) in this paper. Systems designed by the proposed IPRDF are not only fully isolated but also support partial reconfiguration of insulated modules. This allows building secure and dependable systems that can use partial reconfiguration to mitigate from single-event upsets (SEUs) and that are more tolerant to aging and device imperfections. Further, this also allows information assurance applications to benefit from hardware module isolation and run-time reconfigurability. Case studies on isolated Triple Modular Redundancy (TMR) and single-chip cryptographic (SCC) designs are presented to demonstrate capabilities and advantages of the proposed IPRDF methodology.
{"title":"IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs","authors":"K. Pham, E. Horta, Dirk Koch, Anuj Vaishnav, T. Kuhn","doi":"10.1109/MCSoC2018.2018.00018","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00018","url":null,"abstract":"SRAM-based FPGA devices have been used widely in many industrial domains, but only limitedly in secure and safety-critical applications, which have special requirements for the physical implementation, such as module isolation. This is partly due to limited functionality available with current FPGA vendors' tools and flows. To extend FPGA's appearance in secure and safety-critical applications, we propose an alternative flow for isolation design called the Isolated Partial Reconfiguration Design Flow (IPRDF) in this paper. Systems designed by the proposed IPRDF are not only fully isolated but also support partial reconfiguration of insulated modules. This allows building secure and dependable systems that can use partial reconfiguration to mitigate from single-event upsets (SEUs) and that are more tolerant to aging and device imperfections. Further, this also allows information assurance applications to benefit from hardware module isolation and run-time reconfigurability. Case studies on isolated Triple Modular Redundancy (TMR) and single-chip cryptographic (SCC) designs are presented to demonstrate capabilities and advantages of the proposed IPRDF methodology.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133485899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00017
Y. Ben-Asher, Irina Lipov
Wire scaling is becoming problematic for semi-global and global wires in sub 40nm ASIC/VLSI chips. We propose an algorithm that simultaneously minimizes the time T and wire-lengths W for highlevel synthesis from C to Verilog. The program is compiled to a graphs G of arithmetic/logical and memory operations. We developed a formal model wherein the optimal product W × T of a given G can be resolved. The proposed algorithm for general Gs works by recursively decomposing G to either grid-like or tree-like induced sub-graphs and combines their optimal solutions. We have implemented this algorithm in the LLVM compiler and obtained an HLS compiler that successfully minimizes both W × T of the resulting circuits.
{"title":"Unifying Wire and Time Scheduling for Highlevel Synthesis","authors":"Y. Ben-Asher, Irina Lipov","doi":"10.1109/MCSoC2018.2018.00017","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00017","url":null,"abstract":"Wire scaling is becoming problematic for semi-global and global wires in sub 40nm ASIC/VLSI chips. We propose an algorithm that simultaneously minimizes the time T and wire-lengths W for highlevel synthesis from C to Verilog. The program is compiled to a graphs G of arithmetic/logical and memory operations. We developed a formal model wherein the optimal product W × T of a given G can be resolved. The proposed algorithm for general Gs works by recursively decomposing G to either grid-like or tree-like induced sub-graphs and combines their optimal solutions. We have implemented this algorithm in the LLVM compiler and obtained an HLS compiler that successfully minimizes both W × T of the resulting circuits.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114687493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSOC2018.2018.00025
Hamada Mohamed, L. Abdulsalam, Hassan Mohammed
Recommender systems are software tools used to make valuable recommendations to users. Traditionally, recommender systems use information obtained from ratings of an item by users with similar opinions to make recommendations. A user uses a single rating to represent the degree of likeness of an item in traditional recommender systems. Though this approach has reasonably shown a good prediction accuracy, however, the performance of traditional recommender systems is considered inadequate, as users could have different opinions based on some specific features of an item. Multi-criteria recommendation extends the traditional techniques by incorporating ratings for various attributes of the items. It provides better recommendations for users as the system allows the opportunity for users to specify their preferences based on different attributes of user item, which improves prediction accuracy. In this paper, we proposed an aggregation function based method that uses an adaptive genetic algorithm to efficiently incorporate the criteria ratings for improving the accuracy of the multi-criteria recommender system. We carried out an experiment using a dataset for multi-criteria recommendations of movies to users. The experimental result shows that our proposed approach provides better accuracy than the corresponding traditional technique.
{"title":"Adaptive Genetic Algorithm for Improving Prediction Accuracy of a Multi-Criteria Recommender System","authors":"Hamada Mohamed, L. Abdulsalam, Hassan Mohammed","doi":"10.1109/MCSOC2018.2018.00025","DOIUrl":"https://doi.org/10.1109/MCSOC2018.2018.00025","url":null,"abstract":"Recommender systems are software tools used to make valuable recommendations to users. Traditionally, recommender systems use information obtained from ratings of an item by users with similar opinions to make recommendations. A user uses a single rating to represent the degree of likeness of an item in traditional recommender systems. Though this approach has reasonably shown a good prediction accuracy, however, the performance of traditional recommender systems is considered inadequate, as users could have different opinions based on some specific features of an item. Multi-criteria recommendation extends the traditional techniques by incorporating ratings for various attributes of the items. It provides better recommendations for users as the system allows the opportunity for users to specify their preferences based on different attributes of user item, which improves prediction accuracy. In this paper, we proposed an aggregation function based method that uses an adaptive genetic algorithm to efficiently incorporate the criteria ratings for improving the accuracy of the multi-criteria recommender system. We carried out an experiment using a dataset for multi-criteria recommendations of movies to users. The experimental result shows that our proposed approach provides better accuracy than the corresponding traditional technique.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124016492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00024
V. V. Duong, Thuong Nguyen Canh, B. Jeon
In video-based light field image coding, researchers often encode a selected subset of sub-aperture images (SAIs). The subset is heuristically selected as 9x9, 11x11, or 13x13 SAIs out of full 15x15 SAIs. Previous work has focused only on the compression efficiency without light field functionality such as refocusing. This paper evaluates the impact of selecting subset of SAIs not only on the compression quality but also on the quality of refocused light field image. A subset of SAIs is proposed to achieve both comparable compression performance and good quality of the refocused images. Compared to full 15x15 SAIs, our method reduces bitrate by 18.4% in viewpoint of compression and at the same time, maintains a good quality of refocused images.
{"title":"Light Field Image Coding for Efficient Refocusing","authors":"V. V. Duong, Thuong Nguyen Canh, B. Jeon","doi":"10.1109/MCSoC2018.2018.00024","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00024","url":null,"abstract":"In video-based light field image coding, researchers often encode a selected subset of sub-aperture images (SAIs). The subset is heuristically selected as 9x9, 11x11, or 13x13 SAIs out of full 15x15 SAIs. Previous work has focused only on the compression efficiency without light field functionality such as refocusing. This paper evaluates the impact of selecting subset of SAIs not only on the compression quality but also on the quality of refocused light field image. A subset of SAIs is proposed to achieve both comparable compression performance and good quality of the refocused images. Compared to full 15x15 SAIs, our method reduces bitrate by 18.4% in viewpoint of compression and at the same time, maintains a good quality of refocused images.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130545248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00028
Doan Duy, Kiyofumi Tanaka
Recent decades have recognized the popularization of multiprocessor architectures in real-time embedded systems. Real-time task scheduling in such systems has become a challenging problem as a result. In this paper, we are presenting an optimal scheduling algorithm, which can successfully schedule any task sets with no deadline miss if the total utilization of tasks does not exceed the capacity of the involved system. The proposed algorithm called LLA introduces a so-called fixed task-scheduling plan for every time interval that is defined as the time period between two consecutive job releases. At the beginning of each interval, LAA makes the scheduling plan by predicting tasks' requested amount of execution time within the interval and then arranging these amounts to processors appropriately respecting to requirements of scheduling. By this approach, LAA can extremely reduce the number of scheduler invocations to the number of job releases. Furthermore, simulation results show that our algorithm has lower time complexity while retaining the schedulability, task preemption, and task migration competitive to the existing optimal scheduling algorithms.
{"title":"A Novel Task-to-Processor Assignment Approach for Optimal Multiprocessor Real-Time Scheduling","authors":"Doan Duy, Kiyofumi Tanaka","doi":"10.1109/MCSoC2018.2018.00028","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00028","url":null,"abstract":"Recent decades have recognized the popularization of multiprocessor architectures in real-time embedded systems. Real-time task scheduling in such systems has become a challenging problem as a result. In this paper, we are presenting an optimal scheduling algorithm, which can successfully schedule any task sets with no deadline miss if the total utilization of tasks does not exceed the capacity of the involved system. The proposed algorithm called LLA introduces a so-called fixed task-scheduling plan for every time interval that is defined as the time period between two consecutive job releases. At the beginning of each interval, LAA makes the scheduling plan by predicting tasks' requested amount of execution time within the interval and then arranging these amounts to processors appropriately respecting to requirements of scheduling. By this approach, LAA can extremely reduce the number of scheduler invocations to the number of job releases. Furthermore, simulation results show that our algorithm has lower time complexity while retaining the schedulability, task preemption, and task migration competitive to the existing optimal scheduling algorithms.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126385335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00016
Shunsuke Mie, Y. Okuyama, Hiroaki Saito
In this research, we employ spike-based PID controller for Quadcopter control. Quadcopters control their attitude by proportionalintegralderivative (PID) controller for four rotors. General hardware controllers use fixed point computations for PID that consume hardware resources. On the other hand, spikebased PID controller can reduce hardware cost compared with using fixed-point ones. For feasibility tests, we implemented (1) spike-based hardware PID controller for quadcopter attitude control, and (2) an analog-digital mixed simulator for single axis quadcopter model using SystemC-AMS. As a result, we reduced FPG
{"title":"Simplified Quadcopter Simulation Model for Spike-Based Hardware PID Controller using SystemC-AMS","authors":"Shunsuke Mie, Y. Okuyama, Hiroaki Saito","doi":"10.1109/MCSoC2018.2018.00016","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00016","url":null,"abstract":"In this research, we employ spike-based PID controller for Quadcopter control. Quadcopters control their attitude by proportionalintegralderivative (PID) controller for four rotors. General hardware controllers use fixed point computations for PID that consume hardware resources. On the other hand, spikebased PID controller can reduce hardware cost compared with using fixed-point ones. For feasibility tests, we implemented (1) spike-based hardware PID controller for quadcopter attitude control, and (2) an analog-digital mixed simulator for single axis quadcopter model using SystemC-AMS. As a result, we reduced FPG","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114163857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00022
Thao Nguyen Thi Huong, Huy Phi Cong, Xiem HoangVan, Tien Huu Vu
Visual sensor network (VSN) has recently emerged as a promising solution for tremendous range of new vision-sensor based applications, from video surveillance, environmental monitoring to remote sensing. However, the practical VSN currently faces to the visual processing and transmitting problems due to the limitation of power at sensor nodes and the restriction of transmission bandwidth. In this context, the selection of a suitable video compression algorithm is utmost important task for achieving a practical VSN. To address this problem, this paper introduces a practical Raspberry Pi based High Efficiency Video Coding (HEVC) solution for visual sensor networks. The selected video coding solution is one of the most up-to-date compression engines but still achieving the low complexity capability. Experimental results show that the proposed video coding architecture has good compression performance with acceptable complexity performance.
{"title":"A Practical High Efficiency Video Coding Solution for Visual Sensor Network using Raspberry Pi Platform","authors":"Thao Nguyen Thi Huong, Huy Phi Cong, Xiem HoangVan, Tien Huu Vu","doi":"10.1109/MCSoC2018.2018.00022","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00022","url":null,"abstract":"Visual sensor network (VSN) has recently emerged as a promising solution for tremendous range of new vision-sensor based applications, from video surveillance, environmental monitoring to remote sensing. However, the practical VSN currently faces to the visual processing and transmitting problems due to the limitation of power at sensor nodes and the restriction of transmission bandwidth. In this context, the selection of a suitable video compression algorithm is utmost important task for achieving a practical VSN. To address this problem, this paper introduces a practical Raspberry Pi based High Efficiency Video Coding (HEVC) solution for visual sensor networks. The selected video coding solution is one of the most up-to-date compression engines but still achieving the low complexity capability. Experimental results show that the proposed video coding architecture has good compression performance with acceptable complexity performance.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126351865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/MCSoC2018.2018.00039
Andrés Goens, Christian Menard, J. Castrillón
Application requirements for embedded systems are growing rapidly, as is the complexity of systems designed to execute them. A common abstraction used to tame this growing complexity is that of a mapping, which assigns parts of an application to different hardware resources. Modern flows need to explore an intractably large design space of mappings, and be able to quickly find near-optimal mappings for different objectives, sometimes at runtime. With systems featuring thousands of cores in the near horizon, we need methods to make this exploration step truly scalable. In this paper we argue that the mathematical representation of a mapping is central to achieve this. We present different representations and how these could be applied to different contexts and objectives, like complex design-space exploration meta-heuristics or efficient runtime systems.
{"title":"On the Representation of Mappings to Multicores","authors":"Andrés Goens, Christian Menard, J. Castrillón","doi":"10.1109/MCSoC2018.2018.00039","DOIUrl":"https://doi.org/10.1109/MCSoC2018.2018.00039","url":null,"abstract":"Application requirements for embedded systems are growing rapidly, as is the complexity of systems designed to execute them. A common abstraction used to tame this growing complexity is that of a mapping, which assigns parts of an application to different hardware resources. Modern flows need to explore an intractably large design space of mappings, and be able to quickly find near-optimal mappings for different objectives, sometimes at runtime. With systems featuring thousands of cores in the near horizon, we need methods to make this exploration step truly scalable. In this paper we argue that the mathematical representation of a mapping is central to achieve this. We present different representations and how these could be applied to different contexts and objectives, like complex design-space exploration meta-heuristics or efficient runtime systems.","PeriodicalId":413836,"journal":{"name":"2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":"30-31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117190350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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