MTNET: Design and Optimization of a Wireless SOC Test Framework

2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI:10.1109/SOCC.2006.283889

Dan Zhao, Yi Wang

引用次数: 13

Abstract

This paper focuses on a novel self-configurable multihop wireless on-chip micronetwork, namely MTNet, to serve as the test access architecture for testing next generation billion-transistor SoCs. A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Further, a path driven test scheduling algorithm is developed to design and optimize the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of using MTNet for nanoscale SoC testing.

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无线SOC测试框架的设计与优化

本文研究了一种新的自配置多跳无线片上微网络，即MTNet，作为测试下一代十亿晶体管soc的测试接入架构。提出了一种地理路由算法来寻找深嵌核的测试访问路径。在此基础上，提出了一种路径驱动的测试调度算法来设计和优化基于mtnet的SoC测试访问体系结构。大量的仿真研究表明了MTNet在纳米级SoC测试中的可行性和适用性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2006 IEEE International SOC Conference

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