{"title":"An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection","authors":"O. Stroeble, V. Dias, C. Schwoerer","doi":"10.1109/ISSCC.2004.1332794","DOIUrl":null,"url":null,"abstract":"A 10 b 80 MHz pipeline ADC consumes 22 mA at 1.5 V and occupies a die area of 0.3 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology. The ADC is based on a conventional 1.5 b pipeline architecture combined with dynamic-range-doubling and dynamic-reference-selection algorithms.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332794","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 31
Abstract
A 10 b 80 MHz pipeline ADC consumes 22 mA at 1.5 V and occupies a die area of 0.3 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology. The ADC is based on a conventional 1.5 b pipeline architecture combined with dynamic-range-doubling and dynamic-reference-selection algorithms.
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