An 18mb Serial Flash Eeprom For Solid-state Disk Applications

Abstract

High density FLASH EEPROM for solid state disk applications requires minimization of die area while maintaining the flexibility and controllability needed for low cost storage systems. This 18Mb serial FLASH EEPROM utilizes standard 512B sectoring for erase and high parallelism for program and read operations. Erase sector grouping reduces the erase selection circuits by a factor of four over previous designs and a 256 bit programming chunk size increases the program data rate by a factor of four while a shared data latch architecture maintains a similar cell size versus sense area pitch compared to previous designs [l]. In addition, a serial chip selection scheme1 which requires minimal die area enables multiple chip operations to be easily performed. The die is fabricated using a triple poly, single metal, twin well 0.511 CMOS process with memory cell size of 2 . 1 ~ ~ and die size of 396 mils X 290 mils (74 mm2). The split gate, buried n+ source/drain, virtual ground Flash EEPROM memory uses channel hot electron injection for programming and inter poly dielectric tunneling for erase (see figure 1 for cell operation voltages). SERIAL INTERFACE / CHIP SELECTION