Examining the Performance of Low Power – Area Efficient OTA Designs that are Based on Different Current Shunting Techniques

Abstract

This paper provides a comparison between three OTA designs that enhance the performance of the conventional current mirror OTA through shunting current from the main differential pair. In the examined circuits, current shunting is achieved through; constant biased current source transistors in the first design, adaptive biased current shunt transistors through an additional differential pair in the second design, and by a new proposed design that combines the first two techniques together in the third design. The performance of the three designs are tested and optimized on LTspice using 90nm CMOS technology while maintaining stability with a phase margin ≥ 60°. Another major factor examined in this paper is the robustness of the designs against process variations. To test this, all width and length for all transistors were varied by a ±5% using two different tests.