Low Power Spike Detector for Brain-Silicon Interface using Differential Amplitude Slope Operator

Abstract

High-density implantable microelectrode arrays allow to study in-vivo a wide neuron population with the help thousands of integrated electrodes. Such a high electrodes count generates a large amount of data which poses severe challenges in the design of long-term implantable silicon interfaces that rely on a limited power budget and a narrow transmission bandwidth. In such a scenario, reliable spike detectors are needed, as they allow to transmit only the relevant neural information (the neuron action potential) instead of the whole raw recording. Spike detectors based on energy operators provide a good compromise between detection performance and hardware complexity. However, they require a suitable smoothing filter that affects both area occupation and power dissipation. In this paper, we propose a spike detector based on the cascade of two energy operators, without smoothing, and the use of a new simple adaptative threshold calculation. We show that this technique provides good detection metrics compared to previous approaches, for different SNR levels and with several noise models. The proposed system has been synthesized in TSMC 28 nm CMOS technology showing a per-channel area occupation of 0.0021 m$\text{m}^{2}$ with a power consumption of 0.15 $\mu$W, comparing favorably with the state of art of brain machine silicon interfaces.