{"title":"A 3.2 to 4 GHz, 0.25 /spl mu/m CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN","authors":"M. Terrovitis, M. Mack, K. Singh, M. Zargari","doi":"10.1109/ISSCC.2004.1332612","DOIUrl":null,"url":null,"abstract":"A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 /spl mu/m standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 /spl mu/s.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332612","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28
Abstract
A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 /spl mu/m standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 /spl mu/s.
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