Low-power LDPC decoder design exploiting memory error statistics

Abstract

This paper presents a low-power LDPC decoder design by exploiting inherent memory error statistics due to voltage scaling. By analyzing the error sensitivity to the decoding performance at different memory bits and memory locations in the LDPC decoder, the scaled supply voltage is applied to memory bits with high algorithmic error-tolerance capability to reduce the memory power consumption while mitigating the impact on decoding performance. We also discuss how to improve the tolerance to memory errors by increasing the number of iterations in LDPC decoders, and investigate the energy overheads and the decoding throughput loss due to extra iterations. Simulation results of the proposed low-power LDPC decoder technique demonstrate that, by deliberately adjusting the scaled supply voltage to memory bits in different memory locations, the memory power consumption as well as the overall energy consumption of the LDPC decoder can be significantly reduced with negligible performance loss.