Bus performance exploration at CCA and CA levels on QEMU and SystemC-based virtual platform

Abstract

This paper investigates the performance exploration which is affected by different bus arbitration policies of on-chip bus modeling at cycle-count-accurate (CCA) and cycle-accurate (CA) level. All the performance exploration is simulated on the QEMU and SystemC-based virtual platform with a full-fledged operating system up and running by using CCA and CA instruction set simulators as the processor models. To compare the performance at the CCA and CA levels, we use different bus arbitration policies between the processor model and the Direct Memory Access Controller model with two master ports connected by AMBA 2.0 bus modeled at the corresponding level. The statistics at the different levels and different arbitration policies, such as the bus contentions and the bus utilization, are collected by booting up Linux with data movement via DMA. Moreover, the experimental results reveal the tradeoff between the simulation speed and the modeling accuracy of a virtual platform.