Pub Date : 2010-12-01DOI: 10.1109/SOCDC.2010.5682966
Kuan-Chung Chen, C. Chen
A hybrid abstraction of a full system simulation platform can provide flexible hardware-and-software co-verification and co-simulation in early stage of system-on-a-chip development. Being a hybrid abstraction for the simulated system, it has the advantage of faster simulation speed; however, its lack of timing information and no performance-metric synchronization mechanism among the different abstraction levels of the simulation models present troubles in doing performance analysis. To facilitate performance evaluations for hybrid abstraction simulation systems, in this paper, we propose a synchronization profiler to enable cross-abstraction level performance analysis and at the same time retain the fast simulation advantage. This approach allows a design engineer to evaluate not only the interactions between an application and its accelerated hardware but also the corresponding device drivers as well as the OS kernel.
{"title":"A synchronization profiler for hybrid full system simulation platform","authors":"Kuan-Chung Chen, C. Chen","doi":"10.1109/SOCDC.2010.5682966","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682966","url":null,"abstract":"A hybrid abstraction of a full system simulation platform can provide flexible hardware-and-software co-verification and co-simulation in early stage of system-on-a-chip development. Being a hybrid abstraction for the simulated system, it has the advantage of faster simulation speed; however, its lack of timing information and no performance-metric synchronization mechanism among the different abstraction levels of the simulation models present troubles in doing performance analysis. To facilitate performance evaluations for hybrid abstraction simulation systems, in this paper, we propose a synchronization profiler to enable cross-abstraction level performance analysis and at the same time retain the fast simulation advantage. This approach allows a design engineer to evaluate not only the interactions between an application and its accelerated hardware but also the corresponding device drivers as well as the OS kernel.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121260311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/SOCDC.2010.5682923
Yiran Chen, H. Li, Xiaobin Wang, Jongsun Park
Spintronic devices have recently attracted significant attentions in solid state circuit society as a promising device in the applications of nonvolatile memory and emerging circuit design, i.e., memristor-based system. In this paper, we introduce Tunneling magnetoresistance (TMR) device — a popular spintronic device structure and its applications in 1) multi-level cell memory design; 2) memristive devices (memristor); and 3) a special circuit design example — nondestructive self-reference sensing technology.
{"title":"Applications of TMR devices in solid state circuits and systems","authors":"Yiran Chen, H. Li, Xiaobin Wang, Jongsun Park","doi":"10.1109/SOCDC.2010.5682923","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682923","url":null,"abstract":"Spintronic devices have recently attracted significant attentions in solid state circuit society as a promising device in the applications of nonvolatile memory and emerging circuit design, i.e., memristor-based system. In this paper, we introduce Tunneling magnetoresistance (TMR) device — a popular spintronic device structure and its applications in 1) multi-level cell memory design; 2) memristive devices (memristor); and 3) a special circuit design example — nondestructive self-reference sensing technology.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115806216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682960
Haiqing Nan, K. Choi
As CMOS technology is scaled down, transistor density of a chip is increased dramatically, which results in the increasing of the complexity of interconnections. In this paper, a novel design of ternary logic based on carbon nanotube FETs (CNFETs) is proposed and compared with the previous CNFET-based ternary logic designs. Especially, in the proposed CNFET-based ternary logic design, different back biasing voltages and diameters of CNFETs are effectively used to achieve ultra-low power consumption. Extensive simulation results using HSPICE are reported to show that the proposed CNFET-based ternary logic gate reduces leakage current and power delay product (PDP) multiple orders of magnitude compared to the previous CNFET-based ternary logic designs.
{"title":"Novel ternary logic design based on CNFET","authors":"Haiqing Nan, K. Choi","doi":"10.1109/SOCDC.2010.5682960","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682960","url":null,"abstract":"As CMOS technology is scaled down, transistor density of a chip is increased dramatically, which results in the increasing of the complexity of interconnections. In this paper, a novel design of ternary logic based on carbon nanotube FETs (CNFETs) is proposed and compared with the previous CNFET-based ternary logic designs. Especially, in the proposed CNFET-based ternary logic design, different back biasing voltages and diameters of CNFETs are effectively used to achieve ultra-low power consumption. Extensive simulation results using HSPICE are reported to show that the proposed CNFET-based ternary logic gate reduces leakage current and power delay product (PDP) multiple orders of magnitude compared to the previous CNFET-based ternary logic designs.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115094194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682927
T. Zhang, Xin Jin, Chen Liu, Minghui Wang, S. Goto
This paper proposes a region-of-interest (ROI) based H.264/AVC encoder which reduces computational complexity. A proposed fast ROI detection algorithm which can detect face-like regions as ROIs is applied to obtain accurate and small ROI so as to reduce the necessary coding effort of the encoder. The complexity reduction algorithm contains 3 methods: (1) the inter prediction mode selection based on quality difference and ROI status, (2) unequal coding efficiency degradation based on unequal bits allocation, and (3) the ROI boundary enhancement to reduce the coding complexity of center MBs of ROI. Experimental results show that proposed novel ROI detection and complexity reduction scheme can reduce 76.10% simulation time when QP difference between ROI and non-ROI is 20. Compared with previous work, 19.09% of encoding time is further reduced with similar performance degradation.
{"title":"ROI based complexity reduction algorithm for H.264 encoder","authors":"T. Zhang, Xin Jin, Chen Liu, Minghui Wang, S. Goto","doi":"10.1109/SOCDC.2010.5682927","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682927","url":null,"abstract":"This paper proposes a region-of-interest (ROI) based H.264/AVC encoder which reduces computational complexity. A proposed fast ROI detection algorithm which can detect face-like regions as ROIs is applied to obtain accurate and small ROI so as to reduce the necessary coding effort of the encoder. The complexity reduction algorithm contains 3 methods: (1) the inter prediction mode selection based on quality difference and ROI status, (2) unequal coding efficiency degradation based on unequal bits allocation, and (3) the ROI boundary enhancement to reduce the coding complexity of center MBs of ROI. Experimental results show that proposed novel ROI detection and complexity reduction scheme can reduce 76.10% simulation time when QP difference between ROI and non-ROI is 20. Compared with previous work, 19.09% of encoding time is further reduced with similar performance degradation.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128287454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682899
Seungchul Shin, Donghun Heo, Hyungjong Ko, ByeongHa Park
This paper describes an integrated dual-mode DC-DC converter and its seamless auto-mode transition between the pulse frequency modulation (PFM) and the pulse width modulation (PWM), resulting in reduced inductor current peak and output voltage overshoot. The key idea of auto-mode transition is to keep a control voltage level as a constant by forming a negative feedback loop with a compensator in the PFM operation. The DC-DC converter was implemented in the L6LP (65nm) process and achieved maximum 91% of measured efficiency for the load current ranging from 5mA to 200mA.
{"title":"High efficiency DC-DC converter with auto-mode transition for mobile SOC applications","authors":"Seungchul Shin, Donghun Heo, Hyungjong Ko, ByeongHa Park","doi":"10.1109/SOCDC.2010.5682899","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682899","url":null,"abstract":"This paper describes an integrated dual-mode DC-DC converter and its seamless auto-mode transition between the pulse frequency modulation (PFM) and the pulse width modulation (PWM), resulting in reduced inductor current peak and output voltage overshoot. The key idea of auto-mode transition is to keep a control voltage level as a constant by forming a negative feedback loop with a compensator in the PFM operation. The DC-DC converter was implemented in the L6LP (65nm) process and achieved maximum 91% of measured efficiency for the load current ranging from 5mA to 200mA.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134629065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682959
Haiqing Nan, K. Choi
As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32nm technology node. Extensive simulation results using HSPICE are reported to show that the proposed hardened latch design achieves 15X improvement of critical charge (Qcrit) and 6X improvement of charge to power delay product ratio (QPR) compared to the most up to date hardened latch design.
{"title":"Novel soft error hardening design of Nanoscale CMOS latch","authors":"Haiqing Nan, K. Choi","doi":"10.1109/SOCDC.2010.5682959","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682959","url":null,"abstract":"As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32nm technology node. Extensive simulation results using HSPICE are reported to show that the proposed hardened latch design achieves 15X improvement of critical charge (Qcrit) and 6X improvement of charge to power delay product ratio (QPR) compared to the most up to date hardened latch design.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682891
Tse-Chen Yeh, Ming-Chao Chiang
This paper investigates the performance exploration which is affected by different bus arbitration policies of on-chip bus modeling at cycle-count-accurate (CCA) and cycle-accurate (CA) level. All the performance exploration is simulated on the QEMU and SystemC-based virtual platform with a full-fledged operating system up and running by using CCA and CA instruction set simulators as the processor models. To compare the performance at the CCA and CA levels, we use different bus arbitration policies between the processor model and the Direct Memory Access Controller model with two master ports connected by AMBA 2.0 bus modeled at the corresponding level. The statistics at the different levels and different arbitration policies, such as the bus contentions and the bus utilization, are collected by booting up Linux with data movement via DMA. Moreover, the experimental results reveal the tradeoff between the simulation speed and the modeling accuracy of a virtual platform.
{"title":"Bus performance exploration at CCA and CA levels on QEMU and SystemC-based virtual platform","authors":"Tse-Chen Yeh, Ming-Chao Chiang","doi":"10.1109/SOCDC.2010.5682891","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682891","url":null,"abstract":"This paper investigates the performance exploration which is affected by different bus arbitration policies of on-chip bus modeling at cycle-count-accurate (CCA) and cycle-accurate (CA) level. All the performance exploration is simulated on the QEMU and SystemC-based virtual platform with a full-fledged operating system up and running by using CCA and CA instruction set simulators as the processor models. To compare the performance at the CCA and CA levels, we use different bus arbitration policies between the processor model and the Direct Memory Access Controller model with two master ports connected by AMBA 2.0 bus modeled at the corresponding level. The statistics at the different levels and different arbitration policies, such as the bus contentions and the bus utilization, are collected by booting up Linux with data movement via DMA. Moreover, the experimental results reveal the tradeoff between the simulation speed and the modeling accuracy of a virtual platform.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125920832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682879
Jungsuk Kim, G. Wang, W. Dunbar, K. Pedrotti
In this paper, an integrated low-noise patch-clamp amplifier for a solid-state nanopore application is proposed which is composed of three stages: 1) a trans-impedance amplifier (TIA), 2) a voltage-gain amplifier (VGA), and 3) a unity-gain buffer. Because the first stage amplifier makes dominant impacts on gain, bandwidth, noise, stability, and area of the patch-clamp amplifier, in this work, we present the design analysis for the TIA and its optimal feedback resistance. The proposed patch-clamp amplifier has a maximum gain of 152.2dBΩ, an input-referred noise of 11.3pARMS within bandwidth of 10 KHz, and occupies an active die-area of 0.0625mm2. This amplifier is under fabrication in a 0.35μm CMOS 4M2P Process.
{"title":"An integrated patch-clamp amplifier for ultra-low current measurement on solid-state nanopore","authors":"Jungsuk Kim, G. Wang, W. Dunbar, K. Pedrotti","doi":"10.1109/SOCDC.2010.5682879","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682879","url":null,"abstract":"In this paper, an integrated low-noise patch-clamp amplifier for a solid-state nanopore application is proposed which is composed of three stages: 1) a trans-impedance amplifier (TIA), 2) a voltage-gain amplifier (VGA), and 3) a unity-gain buffer. Because the first stage amplifier makes dominant impacts on gain, bandwidth, noise, stability, and area of the patch-clamp amplifier, in this work, we present the design analysis for the TIA and its optimal feedback resistance. The proposed patch-clamp amplifier has a maximum gain of 152.2dBΩ, an input-referred noise of 11.3pARMS within bandwidth of 10 KHz, and occupies an active die-area of 0.0625mm2. This amplifier is under fabrication in a 0.35μm CMOS 4M2P Process.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129151436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682947
Hong Zhu, V. Kursun
SRAM data stability and leakage currents are major concerns in nanometer CMOS technologies. The primary design challenge related to the conventional six-transistor (6T) memory cells is the conflicting set of requirements for achieving read data stability and write ability. A seven-transistor (7T) SRAM cell provides enhanced data stability by isolating the bitlines from data storage nodes during a read operation. The design tradeoffs in a 7T SRAM cell are explored in this paper with a UMC 80nm multi-threshold-voltage CMOS technology that provides a rich set of device options. An electrical performance metric is proposed to evaluate and compare the memory circuits. The multi-threshold-voltage SRAM circuits offering the highest data stability, widest write margin, smallest read and write power consumption, and lowest leakage currents are identified.
{"title":"Data stability enhancement techniques for nanoscale memory circuits: 7T memory design tradeoffs and options in 80nm UMC CMOS technology","authors":"Hong Zhu, V. Kursun","doi":"10.1109/SOCDC.2010.5682947","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682947","url":null,"abstract":"SRAM data stability and leakage currents are major concerns in nanometer CMOS technologies. The primary design challenge related to the conventional six-transistor (6T) memory cells is the conflicting set of requirements for achieving read data stability and write ability. A seven-transistor (7T) SRAM cell provides enhanced data stability by isolating the bitlines from data storage nodes during a read operation. The design tradeoffs in a 7T SRAM cell are explored in this paper with a UMC 80nm multi-threshold-voltage CMOS technology that provides a rich set of device options. An electrical performance metric is proposed to evaluate and compare the memory circuits. The multi-threshold-voltage SRAM circuits offering the highest data stability, widest write margin, smallest read and write power consumption, and lowest leakage currents are identified.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130552929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-01DOI: 10.1109/SOCDC.2010.5682982
Xiaoning Huai, Kijong Lee, C. Kim
A novel image noise reduction filter is developed in wavelet domain. The correlations of intensity and anisotropy of wavelet coefficients in different sub-bands and scales are utilized as features to separate signal from random noise. Dynamic thresholding is used to further increase the sensitivity and discrimination against different noise patterns and standard deviations. Simulation in Matlab is carried out by filtering an AWGN-added sub-set of test images from Kodak image data base and a standard digital Macbeth Color Chart. Average PSNR scores of R, G and B color channels are competitive to bilateral filter and a prominent commercial noise reduction tool Neat Image. In addition, the low computational complexity of threshold operation makes it applicable for low cost implementations in various imaging devices as a real time noise reduction module.
{"title":"Image noise reduction by dynamic thresholding of correlated wavelet intensity and anisotropy","authors":"Xiaoning Huai, Kijong Lee, C. Kim","doi":"10.1109/SOCDC.2010.5682982","DOIUrl":"https://doi.org/10.1109/SOCDC.2010.5682982","url":null,"abstract":"A novel image noise reduction filter is developed in wavelet domain. The correlations of intensity and anisotropy of wavelet coefficients in different sub-bands and scales are utilized as features to separate signal from random noise. Dynamic thresholding is used to further increase the sensitivity and discrimination against different noise patterns and standard deviations. Simulation in Matlab is carried out by filtering an AWGN-added sub-set of test images from Kodak image data base and a standard digital Macbeth Color Chart. Average PSNR scores of R, G and B color channels are competitive to bilateral filter and a prominent commercial noise reduction tool Neat Image. In addition, the low computational complexity of threshold operation makes it applicable for low cost implementations in various imaging devices as a real time noise reduction module.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131653934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：