H. Werker, S. Mechnig, C. Holuigue, C. Ebner, G. Mitteregger, E. Romani, F. Roger, T. Blon, M. Moyal, M. Vena, A. Melodia, J. Fisher, G. de Mercey, H. Geib
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引用次数: 29
Abstract
A single-chip full-rate transceiver in 0.13 /spl mu/m standard CMOS consumes less than 1 W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2 ps rms jitter. A limiting amplifier with a sensitivity of 20 mV at 7 GHz BW enables the CDR to recover data with a BER of <10/sup -12/.
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