Latch-Up Analysis on a 64K Bit Full CMOS Static RAM using a Laser Scanner

Abstract

In order to quantitatively evaluate latch-up sensitivity on scaled CMOS LSIs, an advanced latch-up analyzer with a laser scanner has been developed. As a result of the application of the analyzer to a 64K bit full CMOS static RAM, the analyzer was found to be very useful in latch-up evaluation on CMOS LSIs. Furthermore, high sensitivity regions in the memory cell and a sensitivity distribution in the memory array block, which depend on pattern layout, have been clearly observed on the static RAM.