Synthesis of bundled–data asynchronous pipelines with reduced matched delays on FPGAS

Abstract

Asynchronous paradigm is another option for the project of digital systems. Several design styles can be used, where the micropipeline style is the most suitable one for FPGA platforms because it has a simpler control. It is proposed new pipeline architecture to implement asynchronous systems, in bundled-data micropipeline style, having FPGAs as target devices. One drawback of the bundled-data design is the insertion of delay elements, which increases dissipated power and area. The asynchronous pipeline architecture proposed deals with this problem reducing the number of delay elements. By means of four signal processing benchmarks, it is shown that the proposed architecture can reduces the power dissipation in 21% and 18% respectively, when compared to the MOUSETRAP architecture, and pipeline architecture oriented for FPGAs.