Design Techniques for High Linearity and Dynamic Range Digital to Analog Converters

Abstract

This paper presents recent developments in the design of high linearity and dynamic range digital to analog converters (DAC). It will cover techniques that enable a THD < -120dB and DR > 130dB. Mismatch errors in non-unary DAC can be addressed with mismatch error shaping (MES). Real-time DEM and fixed-transition vector element selection logic (FT-VESL) can mitigate ISI. Moreover, selection algorithms and divide-and-conquer algorithms simplify the hardware implementation. The paper covers distortion mitigation due to analog impairments such as nonlinearities of DAC elements and passives, and routing parasitics. Finally, techniques to suppress reference noise are covered.