A 0.3V 15.6MHz 7T SRAM with Boosted Write and Read Worldlines

Abstract

An ultra-low power 7T -based SRAM system is proposed. The seven-transistor cells are used with write and read wordlines boost assist circuits: WWLB and RWLB. A low power switching PMOS sense amplifier (SPSA) is also presented. The read and write assist circuits utilize charge pumps that generate voltages above VDD and below ground to improve speed of operation. The proposed system works properly at a very low supply voltage equal to 0.3 V. For a 32 Kb system, typical power and energy consumption are 0.147 mW and 3.82 pJ, respectively. The operating frequency is 15.6 MHz and the static noise margin, SNM, is 55mV. All circuits were simulated in Hspice using 28nm CMOS technology devices.