Yield enhancement for WSI array processors using two-and-half-track switches

Abstract

Addresses the enhancement of fabrication yield for arrays of large number of processors. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, the authors are able to develop a reconfiguration algorithm based on the one-and-half-track reconfiguration algorithm. The algorithm can effectively deal with faults on the switches, wires, and connections.<>