A low-power digitally-programmable variable gain amplifier in 65 nm CMOS

Abstract

This paper reports a new topology for a switched-capacitor variable gain amplifier (SC-VGA), which allows discrete-time periodic analog signal generation and in essence fulfils the function of the D/A converter. The proposed circuit exploits a pipelined, cascaded gain stages, which leads to simpler circuit implementation, lower power consumption and reduced kT/C noise, compared to the conventional implementation. The method has the attributes of digital programming and control capability, robustness and reduced area overhead. The two-stage SC-VGA has been fabricated in standard single poly, 65-nm CMOS with the core area of 0.17 mm2 and shows the maximum gain variation of 70 dB and 81 dB linear range, while consuming 11 mW.