Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy

Abstract

Communication plays a crucial role in the design of high performance Multiprocessor Systems-on-Chip (MPSoC). Accordingly, Networks-on-Chip (NoC) have been successfully employed as a solution to deal with communication in complex MPSoCs. NoC-based architectures are characterized by various tradeoffs related to structural characteristics, performance specifications, and application demands. In new technologies, the relative values of wire delays and power consumption are increasing as the number of cores in 2D chips increase. The recent 3D IC technology applied to NoC architectures allows greater device integration and shorter interconnection links, which directly influences the communication performance. Through-Silicon Vias (TSVs) are used for the interconnection between vertical layers of a 3D IC. The drawback is that TSVs are usually very expensive in terms of silicon area, limiting their usage. This work explores the serialization of vertical links, employing a TSV multiplexing scheme for Lasio, a 3D mesh NoC. We implemented and analyzed the impact in network and application latency and in the occupancy of input buffers for a 4×4×4 mesh NoC with different multiplexing degrees, which imply different levels of TSV usage reduction and serialization. Results demonstrate that the proposed scheme allows reducing TSV usage with low performance overhead, pointing to potential benefits of the scheme in 3D NoC-based MPSoCs.