High performance error correcting code of the high-dimensional discrete torus knot

Abstract

The new high-dimensional torus knot code with respect to its geometrical structure has been studied. The special features of the code are presented. (1) The code block is wound up into a small, compact code ball, so the code passes hardly damaged through the channel of a dense shower of error-making disturbances. (2) The torus knot winding works as block-size interleaving, which distributes the received burst errors randomly in the parity check cycles, so the code exhibits excellent burst error correction capability. (3) Majority logic decoding of each code digit based on the erroneous parity lines can be made up of a high-speed logic circuit thanks to the cyclical properties of the code parity check function. The four-dimensional, size-five 4Dm5-code was burned onto a 50-kilogate, 0.6-micron-order VLSI chip. The code block length and the transmission rate are 625 bits and 0.41, respectively. It was operated at a clock speed of 50 MHz, with a throughput of 6.25 Gbps. Through 100000 block trials, it was proven that the chip can perfectly correct a mean BER of 0.021 for burst and random mixed error situations.