A Size Optimization Scheme of SRAM 6T Memory Cell

Abstract

The threshold voltage variations due to the random doping fluctuation and the increasing disturb due to the large number of cells on the chip affect the stability of the read, write, and hold operations of the SRAM circuit. As the smallest size and most numerous module within the chip, the stability of the SRAM memory cell, whether it is used in the configuration chain or in the storage array, is a prerequisite of the whole chip correct function. Most of the articles about the immunity of SRAM circuits focus on changing the circuit structure, such as using 7T, 8T, or 10T memory cells, or adding read and write assist circuits. However, such structural changes can significantly increase the area and the chip leakage current. In this paper, the impact of the size and threshold voltage on its operational stability is analyzed from the perspective of quantitative analysis and simulation. And the optimal SRAM 6T memory cell size is selected based on 28nm CMOS.