The 1:6 phased demultiplexer circuit

Abstract

The behavior of the 1:6 phased demultiplexer (PDMUX6) circuit is analyzed. The circuit demultiplexes the input clock signal into six phased output signals by streaming sets of twelve clock phases. A phase difference equal to the half period of the clock is maintained between consecutive output transitions. The VHDL description of the PDMUX6 cell is given and the simulation and synthesis results are generated. A 2-level tree-like structure is built by applying the phased outputs of the PDMUX6 cell into the corresponding clock inputs of six cell replicas that extend the circuit behavior. The EXOR6 gate is attached to the PDMUX6 cell output ports and is aggregating all the phases that the phased clock signals are carrying while preserving their phase associations.