{"title":"Evolutionary multiobjective design of combinational logic circuits","authors":"C. C. Coello, A. H. Aguirre, B. Buckles","doi":"10.1109/EH.2000.869354","DOIUrl":null,"url":null,"abstract":"In this paper, we propose an evolutionary multiobjective optimization approach to design combinational logic circuits. The idea is to use a population-based technique that considers outputs of a circuit as equality constraints that we aim to satisfy. A small sub-population is assigned to each objective. After one of these objectives is satisfied, its corresponding sub-population is merged with the rest of the individuals in what becomes a joint effort to minimize the total amount of mismatches produced (between the encoded circuit and the truth table). Once a feasible individual is found, all individuals cooperate to minimize its number of gates. The approach seems to reduce the amount of computer resources required to design combinational logic circuits, when compared to our previous research in this area.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"67","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EH.2000.869354","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 67
Abstract
In this paper, we propose an evolutionary multiobjective optimization approach to design combinational logic circuits. The idea is to use a population-based technique that considers outputs of a circuit as equality constraints that we aim to satisfy. A small sub-population is assigned to each objective. After one of these objectives is satisfied, its corresponding sub-population is merged with the rest of the individuals in what becomes a joint effort to minimize the total amount of mismatches produced (between the encoded circuit and the truth table). Once a feasible individual is found, all individuals cooperate to minimize its number of gates. The approach seems to reduce the amount of computer resources required to design combinational logic circuits, when compared to our previous research in this area.