A major problem in the evolutionary design of combinational circuits is the problem of scale. This refers to the design of electronic circuits in which the number of gates required to implement the optimal circuit is too high to search the space of all designs in reasonable time, even by evolution. The reason is twofold: firstly, the size of the search space becomes enormous as the number of gates required to implement the circuit is increased, and secondly, the time required to calculate the fitness of a circuit grows as the size of the truth table of the circuit. This paper studies the evolutionary design of combinational circuits, particularly the three-bit multiplier circuit, in which the basic building blocks are small sub-circuits, modules inferred from other evolved designs. The structure of the resulting fitness landscapes is studied and it is shown that in general the principles of evolving digital circuits are scalable. Thus to evolve digital circuits using modules is faster, since the building blocks of the circuit are sub-circuits rather than two-input gates. This can also be a disadvantage, since the number of gates of the evolved designs grows as the size of the modules used.
{"title":"Scalability problems of digital circuit evolution evolvability and efficient designs","authors":"Vesselin K. Vassilev, J. Miller","doi":"10.1109/EH.2000.869342","DOIUrl":"https://doi.org/10.1109/EH.2000.869342","url":null,"abstract":"A major problem in the evolutionary design of combinational circuits is the problem of scale. This refers to the design of electronic circuits in which the number of gates required to implement the optimal circuit is too high to search the space of all designs in reasonable time, even by evolution. The reason is twofold: firstly, the size of the search space becomes enormous as the number of gates required to implement the circuit is increased, and secondly, the time required to calculate the fitness of a circuit grows as the size of the truth table of the circuit. This paper studies the evolutionary design of combinational circuits, particularly the three-bit multiplier circuit, in which the basic building blocks are small sub-circuits, modules inferred from other evolved designs. The structure of the resulting fitness landscapes is studied and it is shown that in general the principles of evolving digital circuits are scalable. Thus to evolve digital circuits using modules is faster, since the building blocks of the circuit are sub-circuits rather than two-input gates. This can also be a disadvantage, since the number of gates of the evolved designs grows as the size of the modules used.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126635632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Yasunaga, Taro Nakamura, J. H. Kim, I. Yoshihara
We propose a new logic circuit design methodology for kernel-based pattern recognition hardware using a genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.
{"title":"Kernel-based pattern recognition hardware: its design methodology using evolved truth tables","authors":"M. Yasunaga, Taro Nakamura, J. H. Kim, I. Yoshihara","doi":"10.1109/EH.2000.869363","DOIUrl":"https://doi.org/10.1109/EH.2000.869363","url":null,"abstract":"We propose a new logic circuit design methodology for kernel-based pattern recognition hardware using a genetic algorithm. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are evolved to represent kernels in the discrimination functions for pattern recognition. The evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the pattern data set is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the image recognition and the sonar spectrum recognition tasks, and implemented them onto the newly developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates higher recognition accuracy and much faster processing speed than the conventional approaches.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116757804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digital circuit by conventional evolutionary techniques alone, if we are using a subset of the entire truth table for fitness evaluation. The test vector generation problem for testing VLSI (Very Large Scale Integration) suggests that there is no efficient way to determine a training set which assures full correctness of an evolved circuit.
{"title":"The test vector problem and limitations to evolving digital circuits","authors":"Kosuke Imamura, J. Foster, A. Krings","doi":"10.1109/EH.2000.869344","DOIUrl":"https://doi.org/10.1109/EH.2000.869344","url":null,"abstract":"How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digital circuit by conventional evolutionary techniques alone, if we are using a subset of the entire truth table for fitness evaluation. The test vector generation problem for testing VLSI (Very Large Scale Integration) suggests that there is no efficient way to determine a training set which assures full correctness of an evolved circuit.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128314232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the concept of self-testable and self-repairable EPLDs (Electrically Programmable Logic Devices) for high security and safety applications. A design methodology is proposed for self-repairing of a GAL (Generic Array Logic) which is a kind of EPLD. Our fault-locating and fault-repairing architecture uses universal test sets, fault-detecting logic, and self-repairing circuits with spare devices. The design method allows to detect, diagnose, and repair all multiple stuck-at faults which might occur on E/sup 2/CMOS cells in programmable AND plane. A "column replacement" method with extra columns is introduced that discards each faulty column entirely and replaces it with an extra column. The evaluation methodology proves that the self-repairable GAL will last longer in the field.
{"title":"Self-repairable EPLDs: design, self-repair, and evaluation methodology","authors":"Chong H. Lee, M. Perkowski, D. Hall, David S. Jun","doi":"10.1109/EH.2000.869356","DOIUrl":"https://doi.org/10.1109/EH.2000.869356","url":null,"abstract":"This paper describes the concept of self-testable and self-repairable EPLDs (Electrically Programmable Logic Devices) for high security and safety applications. A design methodology is proposed for self-repairing of a GAL (Generic Array Logic) which is a kind of EPLD. Our fault-locating and fault-repairing architecture uses universal test sets, fault-detecting logic, and self-repairing circuits with spare devices. The design method allows to detect, diagnose, and repair all multiple stuck-at faults which might occur on E/sup 2/CMOS cells in programmable AND plane. A \"column replacement\" method with extra columns is introduced that discards each faulty column entirely and replaces it with an extra column. The evaluation methodology proves that the self-repairable GAL will last longer in the field.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127683556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The new Virtex device is for many people the solution to the long term problem of implementing random configurations on digital electronic devices as is required in the paradigm of evolvable hardware. It has previously been shown that evolvable hardware was possible on these devices and that it can be accomplished using partial reconfiguration to speed up the configuration process. Unfortunately the circuit did not have any feedback paths, meaning that any time based circuits could not be implemented. This paper attempts to address this problem by using an array of xc6200 like cells within the Virtex device. Two applications are shown to illustrate the effectiveness of these ideas.
{"title":"Safe intrinsic evolution of Virtex devices","authors":"G. Hollingworth, Steve Smith, A. Tyrrell","doi":"10.1109/EH.2000.869357","DOIUrl":"https://doi.org/10.1109/EH.2000.869357","url":null,"abstract":"The new Virtex device is for many people the solution to the long term problem of implementing random configurations on digital electronic devices as is required in the paradigm of evolvable hardware. It has previously been shown that evolvable hardware was possible on these devices and that it can be accomplished using partial reconfiguration to speed up the configuration process. Unfortunately the circuit did not have any feedback paths, meaning that any time based circuits could not be implemented. This paper attempts to address this problem by using an array of xc6200 like cells within the Virtex device. Two applications are shown to illustrate the effectiveness of these ideas.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128341521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The differences between electronics design through artificial evolution and through conventional methods have the consequence that evolved circuits may take unusual leverage from the physics of their medium of implementation. This can occur even if there is no tractable analytical model to predict how the overall behaviour will emerge from the interactions of the components. This is alluring for single-electron circuit design, and a first case-study is presented: the evolution of a NOR gate. Although the results to date are far from ideal or practical, it appears that the particular thermal energies of the electrons are exploited. Whether desirable or not, this indicates that evolution can explore new kinds of designs not seen before in the literature.
{"title":"Evolutionary design of single electron systems","authors":"A. Thompson, C. Wasshuber","doi":"10.1109/EH.2000.869348","DOIUrl":"https://doi.org/10.1109/EH.2000.869348","url":null,"abstract":"The differences between electronics design through artificial evolution and through conventional methods have the consequence that evolved circuits may take unusual leverage from the physics of their medium of implementation. This can occur even if there is no tractable analytical model to predict how the overall behaviour will emerge from the interactions of the components. This is alluring for single-electron circuit design, and a first case-study is presented: the evolution of a NOR gate. Although the results to date are far from ideal or practical, it appears that the particular thermal energies of the electrons are exploited. Whether desirable or not, this indicates that evolution can explore new kinds of designs not seen before in the literature.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"1784 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129591629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Zebulum, C. C. Santini, H. T. Sinohara, M. Pacheco, M. Vellasco, M. H. Szwarcman
Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and Field Programmable Analog Arrays (FPAAs) constitute the state of the art in the technology of reconfigurable chips, referring to digital and analog devices respectively. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and self-repairing, through automatic reconfiguration. These are essential features for systems that need to perform for a long time in harsh environments such as those employed in space exploration missions. Automatic reconfiguration of field programmable devices may potentially be driven by Evolutionary Computation techniques such as Generic Algorithms. FPAAs have just recently appeared, and most projects are being carried out in universities and research centers. In this article we propose a new model of reconfigurable analog circuit and describe its application in the intrinsic evolution of a simple logic inverter.
{"title":"A reconfigurable platform for the automatic synthesis of analog circuits","authors":"R. Zebulum, C. C. Santini, H. T. Sinohara, M. Pacheco, M. Vellasco, M. H. Szwarcman","doi":"10.1109/EH.2000.869346","DOIUrl":"https://doi.org/10.1109/EH.2000.869346","url":null,"abstract":"Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and Field Programmable Analog Arrays (FPAAs) constitute the state of the art in the technology of reconfigurable chips, referring to digital and analog devices respectively. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and self-repairing, through automatic reconfiguration. These are essential features for systems that need to perform for a long time in harsh environments such as those employed in space exploration missions. Automatic reconfiguration of field programmable devices may potentially be driven by Evolutionary Computation techniques such as Generic Algorithms. FPAAs have just recently appeared, and most projects are being carried out in universities and research centers. In this article we propose a new model of reconfigurable analog circuit and describe its application in the intrinsic evolution of a simple logic inverter.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126575372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose an evolutionary multiobjective optimization approach to design combinational logic circuits. The idea is to use a population-based technique that considers outputs of a circuit as equality constraints that we aim to satisfy. A small sub-population is assigned to each objective. After one of these objectives is satisfied, its corresponding sub-population is merged with the rest of the individuals in what becomes a joint effort to minimize the total amount of mismatches produced (between the encoded circuit and the truth table). Once a feasible individual is found, all individuals cooperate to minimize its number of gates. The approach seems to reduce the amount of computer resources required to design combinational logic circuits, when compared to our previous research in this area.
{"title":"Evolutionary multiobjective design of combinational logic circuits","authors":"C. C. Coello, A. H. Aguirre, B. Buckles","doi":"10.1109/EH.2000.869354","DOIUrl":"https://doi.org/10.1109/EH.2000.869354","url":null,"abstract":"In this paper, we propose an evolutionary multiobjective optimization approach to design combinational logic circuits. The idea is to use a population-based technique that considers outputs of a circuit as equality constraints that we aim to satisfy. A small sub-population is assigned to each objective. After one of these objectives is satisfied, its corresponding sub-population is merged with the rest of the individuals in what becomes a joint effort to minimize the total amount of mismatches produced (between the encoded circuit and the truth table). Once a feasible individual is found, all individuals cooperate to minimize its number of gates. The approach seems to reduce the amount of computer resources required to design combinational logic circuits, when compared to our previous research in this area.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126127489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the design of highly robust integrated circuits, endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. The Embryonics architecture is based on four hierarchical levels of organization: 1) The basic primitive of our system is the molecule, a multiplexer-based element of a novel programmable circuit. 2) A finite set of molecules makes up a cell, essentially a small processor with an associated memory. 3) A finite set of cells makes up an organism, an application-specific multiprocessor system. 4) The organism can itself replicate, giving rise to a population of identical organisms. In the conclusion, we describe our ongoing research efforts to meet three challenges: a scientific challenge, that of implementing the original specifications formulated by John von Neumann; a technical challenge, that of realizing very robust integrated circuits; and a biological challenge, that of attempting to show that the genomes of artificial and natural organisms share common properties.
{"title":"Toward self-repairing and self-replicating hardware: the Embryonics approach","authors":"D. Mange, M. Sipper, A. Stauffer, G. Tempesti","doi":"10.1109/EH.2000.869358","DOIUrl":"https://doi.org/10.1109/EH.2000.869358","url":null,"abstract":"The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the design of highly robust integrated circuits, endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. The Embryonics architecture is based on four hierarchical levels of organization: 1) The basic primitive of our system is the molecule, a multiplexer-based element of a novel programmable circuit. 2) A finite set of molecules makes up a cell, essentially a small processor with an associated memory. 3) A finite set of cells makes up an organism, an application-specific multiprocessor system. 4) The organism can itself replicate, giving rise to a population of identical organisms. In the conclusion, we describe our ongoing research efforts to meet three challenges: a scientific challenge, that of implementing the original specifications formulated by John von Neumann; a technical challenge, that of realizing very robust integrated circuits; and a biological challenge, that of attempting to show that the genomes of artificial and natural organisms share common properties.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126191102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A more general development of a building block for intrinsic evolution of analogue hardware is introduced and explained. A wide variety of linear and non-linear instantaneous and time-related characteristics can be created with the block, and blocks may be interconnected in a very general way. Examples of different types of achievable characteristic are shown and results of a comparison of different search algorithms in intrinsically evolving a linear band-pass filter are presented.
{"title":"Behaviour of a building block for intrinsic evolution of analogue signal shaping and filtering circuits","authors":"S. J. Flockton, K. Sheehan","doi":"10.1109/EH.2000.869349","DOIUrl":"https://doi.org/10.1109/EH.2000.869349","url":null,"abstract":"A more general development of a building block for intrinsic evolution of analogue hardware is introduced and explained. A wide variety of linear and non-linear instantaneous and time-related characteristics can be created with the block, and blocks may be interconnected in a very general way. Examples of different types of achievable characteristic are shown and results of a comparison of different search algorithms in intrinsically evolving a linear band-pass filter are presented.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126889422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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