Parallel clocking: a multi-phase clock-network for 10GHz SoC

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332735

K. Nose, M. Mizuno

引用次数: 5

Abstract

The realization of SoCs operating at 10GHz and multiple frequency IP-cores is possible using parallel clocking. With 2.5GHz 4-phase parallel clocking, the skew reduction circuits and multi-phase flip-flops successfully operate at 10GHz.

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并行时钟:用于10GHz SoC的多相时钟网络

使用并行时钟可以实现工作在10GHz和多频ip核的soc。采用2.5GHz 4相并行时钟，斜降电路和多相触发器成功地工作在10GHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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