{"title":"Small Area Footprint FPGA Architecture for Approximate atan2(a, b) Algorithm","authors":"B. Kumar, K. Sarawadekar","doi":"10.1109/UPCON56432.2022.9986456","DOIUrl":null,"url":null,"abstract":"Arctangent or inverse tangent function has numerous applications like gradient-based feature extraction, phase noise determination, range rate measurement etc. This paper presents a small area footprint hardware architecture for computing the arctangent of a complex number. The proposed method uses numerical approximation and LUTs used to improve the accuracy of the results obtained. Single-precision floating-point representation is used to implement the proposed design and the results demonstrate very good accuracy with an error of about ±0.0004 radian with $256\\times 32$ bits memory size. The proposed architecture is implemented on Nexys4 DDR FPGA board using Verilog and it operates at 19.8 MHz. Integrated Logic Analyzer (ILA) is used to debug and validate the proposed design. Further, it is observed that results obtained with the proposed design are in agreement with the Matlab simulation results.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/UPCON56432.2022.9986456","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Arctangent or inverse tangent function has numerous applications like gradient-based feature extraction, phase noise determination, range rate measurement etc. This paper presents a small area footprint hardware architecture for computing the arctangent of a complex number. The proposed method uses numerical approximation and LUTs used to improve the accuracy of the results obtained. Single-precision floating-point representation is used to implement the proposed design and the results demonstrate very good accuracy with an error of about ±0.0004 radian with $256\times 32$ bits memory size. The proposed architecture is implemented on Nexys4 DDR FPGA board using Verilog and it operates at 19.8 MHz. Integrated Logic Analyzer (ILA) is used to debug and validate the proposed design. Further, it is observed that results obtained with the proposed design are in agreement with the Matlab simulation results.