Y. Joly, J. Delalleau, L. Lopez, J. Portal, H. Aziza, Y. Bert, F. Julien, P. Fornara
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引用次数: 1
Abstract
This paper demonstrates how poly-Silicon gate pre-doping implantation impacts MOS matching performances. Measurements are performed on test structures (MOS pairs / capacitors) and analog circuits, using five different processes with pre-doping implantation energy variation (from 35 to 10 KeV) and tilt variation (7° and 25°). TCAD simulations validate a channel counter-doping due to high pre-doping implantation energy causing mismatch degradation.
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