Design of a 90nm 4-CPU 4320MIPS SoC with individually managed frequency and 2.4GB/s multi-master on-chip interconnect

Abstract

We have developed a 97.6 mm2 SoC that includes four SuperHtrade architecture CPUs and a DDR-2 controller with 90-nm CMOS for high-performance embedded applications. These four 600 MHz CPUs are identical and each has a floating point unit, 32/32 KB cache memory, and 152 KB local memory. CPUs totally achieve performance of 4320MIPS. Main on-chip 300 MHz 64-bit bus manages processors access and another dedicated connection holds cache coherency operation. Considering varying processing load, this chip targets both low power consumption (proportional to processing load), and constant on-chip bandwidth. Each processor can be operated different frequencies while keeping on-chip bus frequency constant. With utilizing this individual core clock distribution scheme, the following designs have been developed: (i) frequency transition control that permits on-chip bus access of other bus master, (11) light-sleep mode that maintains cache coherency control, (iii) cache snoop control logic that holds cache coherency between multiple frequency processors. The main on-chip interconnect (bus) connects four-processor and other on-chip IPs. The numbers of access master and access slave increase due to processor number. Standard-Vth (against high-Vth) cell usage and layout control achieved 300-MHz multi-master operation.