{"title":"An energy-efficient power-gating adiabatic circuits using transmission gate switches","authors":"D. Zhou, Jianping Hu, Huiying Dong","doi":"10.1109/ICASIC.2007.4415588","DOIUrl":null,"url":null,"abstract":"This paper presents a new power-gating technique for adiabatic circuits to reduce energy loss during idle state. The power-gating switches based on DTGAL (dual transmission gate adiabatic logic) circuits are used to detach adiabatic logic blocks from power-clocks. The energy overhead optimization for the proposed power-gating scheme is investigated. The 8-bit full adders based on DTGAL circuits are verified using the proposed power-gating technique. All circuits are verified using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. Energy loss is reduced greatly by shutting down idle adiabatic logic blocks.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415588","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper presents a new power-gating technique for adiabatic circuits to reduce energy loss during idle state. The power-gating switches based on DTGAL (dual transmission gate adiabatic logic) circuits are used to detach adiabatic logic blocks from power-clocks. The energy overhead optimization for the proposed power-gating scheme is investigated. The 8-bit full adders based on DTGAL circuits are verified using the proposed power-gating technique. All circuits are verified using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. Energy loss is reduced greatly by shutting down idle adiabatic logic blocks.