Comprehensive investigation on mechanical strain induced performance boosts in LDMOS

Abstract

In this paper, we have comprehensively investigated the performance of LDMOS under mechanical strain. The electrical properties of nLDMOS under uniaxial tensile (UT) strain along channel direction are examined thoroughly. We find that the nLDMOS with longer gate length (Lg) is more preferred for strain. Both lateral electric field (Vd) and vertical electric field (Vg) play an important role on the strain effects. The piezoresistance coefficients of nLDMOS are evaluated for the first time. Neglectable breakdown voltage (Vbd) degradation is observed with the 4.4% drain current (Id) increase under UT strain. Finally, the biaxial tensile strain and uniaxial compressive strain parallel to channel are proved to be most efficient for nLDMOS and pLDMOS with 8.8% and 14.5% Ron reduction, respectively.