Evaluating template-based instruction compression on transport triggered architectures

Abstract

Program code size has become a critical design constraint of embedded systems. Code compression is one of the approaches to reduce the program code size; it results in smaller memories and reduced cost of the chip. In this paper, a code compression method based on instruction templates has been used to improve the code density transport triggered architecture. Six applications taken from different application domains are used for benchmarking. The obtained results show significant improvements in code density.