Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage

Abstract

We present a design-for-testability (DFT) technique for increasing the effectiveness of LFSR reseeding for unmodeled defects. The proposed method relies on seed selection using the output-deviations metric and the on-chip augmentation of seeds using simple bit-operations. Simulation results for benchmark circuits show that compared to LFSR reseeding using output deviations alone, the proposed method provides higher coverage for transition-delay and bridging faults, and steeper coverage ramp-up for these faults for the same number of seeds. For the same pattern count (and much fewer seeds), the proposed method provides comparable unmodeled defect coverage. In all cases, complete coverage of modeled stuck-at faults is obtained. We therefore conclude that high test quality can be obtained with the proposed LFSR reseeding method using a smaller number of seeds.