H. Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue
Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancement of LSIs and selective hardening for LSI systems. In this paper, we propose test generation models for threshold test generation. Using the proposed models, we can efficiently identify acceptable faults and generate test patterns for unacceptable faults with a general test generation algorithm, i.e., without a test generation algorithm specialized for threshold testing. Experimental results show that our approach is practically effective.
{"title":"A Practical Approach to Threshold Test Generation for Error Tolerant Circuits","authors":"H. Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue","doi":"10.1109/ATS.2009.19","DOIUrl":"https://doi.org/10.1109/ATS.2009.19","url":null,"abstract":"Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancement of LSIs and selective hardening for LSI systems. In this paper, we propose test generation models for threshold test generation. Using the proposed models, we can efficiently identify acceptable faults and generate test patterns for unacceptable faults with a general test generation algorithm, i.e., without a test generation algorithm specialized for threshold testing. Experimental results show that our approach is practically effective.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115001150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jun-Jie Zhu, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh
Embedded processors are ubiquitous in today’s system-on-chip design. In addition to designing digital signal processors (DSPs) for various applications, developing efficient test methods with little overhead and desired fault coverage for DSPs are also crucial and practical. Compared with the scan-based test methods, the software-based self-test (SBST) method does not suffer from area overhead and performance degradation, and can provide at-speed test for DSPs with the potential drawbacks of lower fault coverage and a larger amount of test vectors. This paper explores techniques to improve the fault coverage of SBST methods for the developed DSP core with instructions fully compatible with those of the TI TMS320C54x. Experimental results exhibit that applying the developed SBST test flow obtains more than 96% fault coverage for our DSP core, which is higher than the reported values in related works.
{"title":"Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors","authors":"Jun-Jie Zhu, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh","doi":"10.1109/ATS.2009.30","DOIUrl":"https://doi.org/10.1109/ATS.2009.30","url":null,"abstract":"Embedded processors are ubiquitous in today’s system-on-chip design. In addition to designing digital signal processors (DSPs) for various applications, developing efficient test methods with little overhead and desired fault coverage for DSPs are also crucial and practical. Compared with the scan-based test methods, the software-based self-test (SBST) method does not suffer from area overhead and performance degradation, and can provide at-speed test for DSPs with the potential drawbacks of lower fault coverage and a larger amount of test vectors. This paper explores techniques to improve the fault coverage of SBST methods for the developed DSP core with instructions fully compatible with those of the TI TMS320C54x. Experimental results exhibit that applying the developed SBST test flow obtains more than 96% fault coverage for our DSP core, which is higher than the reported values in related works.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116934929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Chakravadhanula, V. Chickermane, B. Keller, Patrick R. Gallagher, A. Uzzaman
Designs using advanced low power techniques like Multi- Supply Multi-Voltage and Power Shutoff bring with them a new set of challenges that manufacturing test must deal with carefully. These designs have low power components – isolation cells, retention flops, level shifters, power switches, etc., – that must be tested not only structurally but also addressing their behavior across multiple power modes. This paper describes the challenges in testing the key low power components and proposes novel solutions. The defective behavior of state retention logic is modeled to enable fault grading. ATPG modeling of defective behavior of isolation logic and level shifters is described for designs that support multiple supply voltages and power shutoff. The solutions are supported by experimental results on industrial designs.
{"title":"Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?","authors":"K. Chakravadhanula, V. Chickermane, B. Keller, Patrick R. Gallagher, A. Uzzaman","doi":"10.1109/ATS.2009.80","DOIUrl":"https://doi.org/10.1109/ATS.2009.80","url":null,"abstract":"Designs using advanced low power techniques like Multi- Supply Multi-Voltage and Power Shutoff bring with them a new set of challenges that manufacturing test must deal with carefully. These designs have low power components – isolation cells, retention flops, level shifters, power switches, etc., – that must be tested not only structurally but also addressing their behavior across multiple power modes. This paper describes the challenges in testing the key low power components and proposes novel solutions. The defective behavior of state retention logic is modeled to enable fault grading. ATPG modeling of defective behavior of isolation logic and level shifters is described for designs that support multiple supply voltages and power shutoff. The solutions are supported by experimental results on industrial designs.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121359501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a low-cost output response analyzer (ORA) for the built-in-self-test (BIST) Σ-Δ ADC based on the controlled sine wave fitting (CSWF) method. The ADC under test (AUT) is composed of a design-for-digital-testability (DfDT) second-order Σ-Δ modulator and a decimation filter. The CSWF BIST procedure requests an ORA to accept the output of the AUT and calculates the offset, the amplitude of the stimulus tone response, and the total-harmonic-distortion-and-noise (THD+N) power in three successive BIST steps respectively. Each BIST step needs an accumulator to conduct the specified BIST function. By sharing an accumulator for every BIST step, the proposed ORA design contains only 1.9k gates without loss of computational accuracy. The hardware is only 34% of the original design. Simulation results show that the proposed ORA presents accurate SNDR results for the 1 kHz tests.
{"title":"A Low-Cost Output Response Analyzer for the Built-in-Self-Test Σ-Δ Modulator Based on the Controlled Sine Wave Fitting Method","authors":"Shao-Feng Hung, Hao-Chiao Hong, Sheng-Chuan Liang","doi":"10.1109/ATS.2009.88","DOIUrl":"https://doi.org/10.1109/ATS.2009.88","url":null,"abstract":"This paper proposes a low-cost output response analyzer (ORA) for the built-in-self-test (BIST) Σ-Δ ADC based on the controlled sine wave fitting (CSWF) method. The ADC under test (AUT) is composed of a design-for-digital-testability (DfDT) second-order Σ-Δ modulator and a decimation filter. The CSWF BIST procedure requests an ORA to accept the output of the AUT and calculates the offset, the amplitude of the stimulus tone response, and the total-harmonic-distortion-and-noise (THD+N) power in three successive BIST steps respectively. Each BIST step needs an accumulator to conduct the specified BIST function. By sharing an accumulator for every BIST step, the proposed ORA design contains only 1.9k gates without loss of computational accuracy. The hardware is only 34% of the original design. Simulation results show that the proposed ORA presents accurate SNDR results for the 1 kHz tests.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125495756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Keller, Dale Meehl, A. Uzzaman, Richard Billings
This paper shows a way to define a partially-exhaustive gate transition fault model for use in catching defects that escape when using more traditional fault models. We define the gate-level transitions ATPG must create for this fault model and how this may catch un-modeled defects. Future work will analyze results of applying tests generated using this fault model against a commercial chip design.
{"title":"A Partially-Exhaustive Gate Transition Fault Model","authors":"B. Keller, Dale Meehl, A. Uzzaman, Richard Billings","doi":"10.1109/ATS.2009.62","DOIUrl":"https://doi.org/10.1109/ATS.2009.62","url":null,"abstract":"This paper shows a way to define a partially-exhaustive gate transition fault model for use in catching defects that escape when using more traditional fault models. We define the gate-level transitions ATPG must create for this fault model and how this may catch un-modeled defects. Future work will analyze results of applying tests generated using this fault model against a commercial chip design.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129531064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Michihiro Shintani, T. Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, K. Hatayama, T. Aikyo, K. Masu
The continuing miniaturization of LSI dimension is causing the increase of process-related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.
{"title":"An Adaptive Test for Parametric Faults Based on Statistical Timing Information","authors":"Michihiro Shintani, T. Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, K. Hatayama, T. Aikyo, K. Masu","doi":"10.1109/ATS.2009.90","DOIUrl":"https://doi.org/10.1109/ATS.2009.90","url":null,"abstract":"The continuing miniaturization of LSI dimension is causing the increase of process-related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129338196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li
The self wide-range (26%~76%), fine-scale (34ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.
{"title":"Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test","authors":"Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li","doi":"10.1109/ATS.2009.72","DOIUrl":"https://doi.org/10.1109/ATS.2009.72","url":null,"abstract":"The self wide-range (26%~76%), fine-scale (34ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123371936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Large test data volume and excessive testing power are two strict challenges for VLSI testing. This paper presents a deterministic BIST using multiple LFSRs to generate the low power test set. Experimental results show, the two problems, especially in the reduction of testing power, can be significantly improved with limited hardware overhead.
{"title":"Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing","authors":"Lung-Jen Lee, W. Tseng, Rung-Bin Lin, Chi-Wei Yu","doi":"10.1109/ATS.2009.50","DOIUrl":"https://doi.org/10.1109/ATS.2009.50","url":null,"abstract":"Large test data volume and excessive testing power are two strict challenges for VLSI testing. This paper presents a deterministic BIST using multiple LFSRs to generate the low power test set. Experimental results show, the two problems, especially in the reduction of testing power, can be significantly improved with limited hardware overhead.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131653676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets, which distinguish pairs of single stuck-at faults n times, to enhance the probability of distinguishing unmodeled defects. The basis for the use of n-distinguishing test sets to enhance defect diagnosis is similar to that for using n-detection test sets to improve the detection of unmodeled defects. We use a heuristic to target a subset of fault pairs for n-distinguishing in order to improve the efficacy of the patterns generated for aiding diagnosis. Experimental results on the larger ISCAS benchmark circuits are presented to demonstrate the improvements in defect diagnostic resolution due to the use of n-distinguishing test sets. We use randomly selected resistive bridges to represent unmodeled defects. The experimental results also show that the coverage of unmodeled defects by n-distinguishing test sets is similar to that by n-detection test sets even though the number of n-distinguishing tests is typically smaller. This suggests the possibility of using n-distinguishing test sets in place of n-detection test sets in manufacturing test.
{"title":"N-distinguishing Tests for Enhanced Defect Diagnosis","authors":"Gang Chen, J. Rajski, S. Reddy, I. Pomeranz","doi":"10.1109/ATS.2009.47","DOIUrl":"https://doi.org/10.1109/ATS.2009.47","url":null,"abstract":"Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets, which distinguish pairs of single stuck-at faults n times, to enhance the probability of distinguishing unmodeled defects. The basis for the use of n-distinguishing test sets to enhance defect diagnosis is similar to that for using n-detection test sets to improve the detection of unmodeled defects. We use a heuristic to target a subset of fault pairs for n-distinguishing in order to improve the efficacy of the patterns generated for aiding diagnosis. Experimental results on the larger ISCAS benchmark circuits are presented to demonstrate the improvements in defect diagnostic resolution due to the use of n-distinguishing test sets. We use randomly selected resistive bridges to represent unmodeled defects. The experimental results also show that the coverage of unmodeled defects by n-distinguishing test sets is similar to that by n-detection test sets even though the number of n-distinguishing tests is typically smaller. This suggests the possibility of using n-distinguishing test sets in place of n-detection test sets in manufacturing test.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133694840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, K. Namba, Hideo Ito
This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area, smaller data volume, and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18μm process shows that the area overhead of the proposed scan design is 32.2% smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively.
{"title":"A Delay Measurement Technique Using Signature Registers","authors":"Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, K. Namba, Hideo Ito","doi":"10.1109/ATS.2009.54","DOIUrl":"https://doi.org/10.1109/ATS.2009.54","url":null,"abstract":"This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area, smaller data volume, and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18μm process shows that the area overhead of the proposed scan design is 32.2% smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123632673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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