An on-chip load model for off-chip PDN analysis considering interdependency between supply voltage, current profile and clock latency

Abstract

Simple yet accurate on-chip load model is demanded for off-chip power delivery network (PDN) design and verification. Conventionally, a current source that represents a short chip operation period is used for this purpose, but it cannot consider the interdependency between supply voltage, load current and clock latency. The ignorance of this interdependency could mislead off-chip PDN design causing over- and under-design. To address this issue, this paper proposes an on-chip load model with Verilog-A that can replay the load current and clock latency under dynamic supply noise. The model is expanded to support different chip operation modes, and it can be used as a sub-model to construct a large chip model. Experiment shows over 200X run-time improvement comparing with full SPICE netlist simulation. We also confirm that the current profile, power consumption, and clock latency are closely correlated.