Analysis of CMOS-Memristive Analog Multiplier Design

Abstract

The conventional CMOS analog multiplier circuits used in different architectures suffer from linearity problems, low processing speed, low accuracy large on-chip area and high power consumption. One of the possible solution to overcome these problems is to use memristive components in analog multiplier design. This paper proposes a CMOS analog multiplier design with memristive components. The aim of the paper is to compare the power consumption and overall characteristic of the memristor-based multiplier with the performance conventional CMOS multiplier circuit. The circuit is designed using TSMC 180nm CMOS technology, and the simulations are conducted in SPICE. The effects of channel modulation and temperature on the multiplier performance are discussed.