An analog front end for 2400b/s split-band full-duplex modems

K. Yamamoto, H. Ohtake, J. Maruyama
{"title":"An analog front end for 2400b/s split-band full-duplex modems","authors":"K. Yamamoto, H. Ohtake, J. Maruyama","doi":"10.1109/ISSCC.1986.1156914","DOIUrl":null,"url":null,"abstract":"A single chip analog front end for 1200 and 2400b/s modems that includes A/D and D/A converters, processor interfaces, 50 poles of filtering and equalization, tone generators, and a call progress detection filter, will be discribed. A 5μm CMOS implementation requires a die area of 6.5×6.37mm2.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156914","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

A single chip analog front end for 1200 and 2400b/s modems that includes A/D and D/A converters, processor interfaces, 50 poles of filtering and equalization, tone generators, and a call progress detection filter, will be discribed. A 5μm CMOS implementation requires a die area of 6.5×6.37mm2.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
模拟前端2400b/s分带全双工调制解调器
将描述用于1200和2400b/s调制解调器的单芯片模拟前端,包括A/D和D/A转换器,处理器接口,50极滤波和均衡,音调发生器和呼叫进度检测滤波器。5μm CMOS实现所需的芯片面积为6.5×6.37mm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A digital processor for decoding of composite TV signals using adaptive filtering A flat-panel display control IC with 150V drivers A 50Mb/s CMOS LED driver circuit A CMOS electrically reprogrammable ASIC with multi-level random logic capabilities A 15ns CMOS 64K RAM
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1