Hardware Design and Implementation of a Wireless Chaotic Text Encryption Scheme

Abstract

This work proposes a chaotic text encryption scheme implemented in a microcontroller device. Initially, a chaotic 1D map is proposed and studied through its bifurcation diagrams and Lyapunov exponent diagram. The map showcases a constant chaotic behavior, which makes it suitable for use in encrytption. Based on this map, a pseudo random bit generator is designed. This generator is then used as a source of deterministic randomness, in order to encrypt a text message, using XOR. The complete scheme is then implemented in two microcontroller devices that can each implement the encryption and decryption procedures. This allows the safe transmission of an information text between the two devices, and can be the basis for further experimentation.