Consideration of the Flit Size for Deflection Routing based Network-on-Chips

Abstract

Bufferless deflection routing enables energy and hardware efficient Network-on-Chips (NoCs). However, due to the lack of buffers, packet switching can not be deployed for such NoCs. Therefore, it is crucial to determine an appropriate flit size and link width, which can be considerably larger compared to packet switched NoCs. In this work, we investigate the effect of the flit size on hardware costs and on performance for NoCs based on a permutation network and additionally on deflection routing. We show that hardware requirements for a permutation network based router increase linearly. The performance decreases exponentially with smaller link widths, however a moderate reduction of the link width can be an option.