Instruction Level Power Analysis for Low Power VLSI Applications

Abstract

Power is increasingly becoming a design constraint for low power VLSI circuits. Power consumed by the hardware is well known and understood. There are various standard methods to measure and evaluate the power consumed by the hardware in a circuit/system. And also there are well established techniques to reduce the power in a VLSI device. But Power consumption of the device during the execution of the software program is becoming an important issue in designing low power VLSI devices/circuits. This so called software power could be reduced by many techniques. By manipulating the instructions in a code, software related power could be reduced. This work brings about the efficient scheme for instruction level software power analysis for TMS320C6713 DSP processor. This is achieved by measuring the average instantaneous current drawn and hence power dissipated by the processor as it repeatedly executes the set of instructions. Experimental results show that the difference up to 0.2% between the estimated and measured current values.