Self-termination scheme for high-speed chip-to-chip data communication

P. Vijaya Sankara Rao, P. Mandal
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引用次数: 1

Abstract

In this work we propose self-termination scheme for high-speed current-mode differential signaling. This scheme eliminates the need of any dedicated passive terminator avoiding signal reflection both at the transmitter and receiver. We present fully differential, high speed transmitter/receiver(Tx/Rx) pair suitable for this self-terminated differential current-mode signaling scheme. We propose high-speed, power efficient self terminating transmitter with modified Cherry-Hooper topology. Also propose, self terminated, differential current-mode receiver realized by modified regulated gate cascode (RGC) based common-source (CS) trans-impedance amplifier (TIA) with folded active inductor peaking. The transmitter and receiver circuits are implemented in 1.8-V, 0.18-µm Digital CMOS technology with an ƒT of 27-GHz. The designed transmitter and receiver circuits, handle data rates up-to 8-Gb/s for the targeted BER of 10−12, while transmitting the data over backplane FR4 PCB trace of length 7.5-inch. The power consumed in the transmitter and receiver circuits is 10.31-mW and 10.17-mW respectively at 8-Gb/s data rate.
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高速片对片数据通信的自终止方案
在这项工作中,我们提出了高速电流模式差分信号的自终止方案。该方案不需要任何专用的无源终止器,避免了发送端和接收端的信号反射。我们提出了适用于这种自端差分电流模式信号方案的全差分高速发送/接收(Tx/Rx)对。我们提出了一种采用改进的Cherry-Hooper拓扑结构的高速、节能的自终端发射机。并提出了一种自终止差分电流模式接收器,该接收器采用折叠有源电感峰值,基于改进的调节门级联码(RGC)的共源(CS)反阻抗放大器(TIA)实现。发射器和接收器电路采用1.8 v, 0.18µm数字CMOS技术,ƒT频率为27 ghz。设计的发送和接收电路可以处理高达8gb /s的数据速率,目标误码率为10−12,同时通过长度为7.5英寸的背板FR4 PCB走线传输数据。在8gb /s数据速率下,发送和接收电路的功耗分别为10.31 mw和10.17 mw。
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