Aihua Dong, J. Xiong, S. Mitra, Wei Liang, R. Gauthier, A. Loiseau
{"title":"Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node","authors":"Aihua Dong, J. Xiong, S. Mitra, Wei Liang, R. Gauthier, A. Loiseau","doi":"10.23919/EOS/ESD.2018.8509689","DOIUrl":null,"url":null,"abstract":"ESD design window for mainstream bulk and SOI planar/FinFET technologies across 350nm7nm node are compared for the first time. 100ns TLP and 1ns vfTLP characteristics of Vgox, and Vt1, and It2 of various logic and I/O FETs are presented anddiscussed. Expanding the design window by utilizing series resistance within I/O driversis discussed.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EOS/ESD.2018.8509689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
ESD design window for mainstream bulk and SOI planar/FinFET technologies across 350nm7nm node are compared for the first time. 100ns TLP and 1ns vfTLP characteristics of Vgox, and Vt1, and It2 of various logic and I/O FETs are presented anddiscussed. Expanding the design window by utilizing series resistance within I/O driversis discussed.
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