Transient Error Detection and Recovery in Processor Pipelines

Abstract

Transient errors, due to cosmic radiations, are a major reliability barrier for modern processors. The vulnerability of processor cores to transient errors grows exponentially with technology scaling. To meet reliability constraints in a cost-effective way, it is critical to localize the effects of these errors and prevent them from propagating to other parts of the system. In this paper, we present a methodology to provide low-cost transient error detection and recovery in processor pipelines. Using the approach transient errors can be detected and the processor can recover from the effects without adding additional structures outside the pipeline. In this technique, we use error control coding for detection and correction of error in pipeline stages. We also reuse the hazard detection mechanisms commonly used in modern processor pipelines for efficient and transparent error recovery. Experimental results confirm the efficiency of the proposed technique in terms of reliability (100% error detection, correction and recovery) and overhead (15% area and 25% delay overhead).