{"title":"Carry-Select Adder","authors":"O. Bedrij","doi":"10.1109/IRETELC.1962.5407919","DOIUrl":null,"url":null,"abstract":"A large, extremely fast digital adder with sum selection and multiple-radix carry is described. Boolean expressions for the operation are included. The amount of hardware and the logical delay for a 100-bit ripple-carry adder and a carry-select adder are compared. The adder system described increases the speed of the addition process by reducing the carry-propagation time to the minimum commensurate with economical circuit design. The problem of carry-propagation delay is overcome by independently generating multiple-radix carries and using these carries to select between simultaneously generated sums. In this adder system, the addend and augend are divided into subaddend and subaugend sections that are added twice to produce two subsums. One addition is done with a carry digit forced into each section, and the other addition combines the operands without the forced carry digit. The selection of the correct, or true, subsum from each of the adder sections depends upon whether or not there actually is a carry into that adder section.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"479","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IRE Trans. Electron. Comput.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRETELC.1962.5407919","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 479
Abstract
A large, extremely fast digital adder with sum selection and multiple-radix carry is described. Boolean expressions for the operation are included. The amount of hardware and the logical delay for a 100-bit ripple-carry adder and a carry-select adder are compared. The adder system described increases the speed of the addition process by reducing the carry-propagation time to the minimum commensurate with economical circuit design. The problem of carry-propagation delay is overcome by independently generating multiple-radix carries and using these carries to select between simultaneously generated sums. In this adder system, the addend and augend are divided into subaddend and subaugend sections that are added twice to produce two subsums. One addition is done with a carry digit forced into each section, and the other addition combines the operands without the forced carry digit. The selection of the correct, or true, subsum from each of the adder sections depends upon whether or not there actually is a carry into that adder section.
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